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* Fix codying style broken by recent libfdt syncMasahiro Yamada2016-10-24-4/+4
| | | | | | | | | Commit b02e4044ff8e ("libfdt: Bring in upstream stringlist functions") broke codying style in some places especially by inserting an extra whitespace before fdt_stringlist_count(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* pinctrl: uniphier: fix unused-const-variable warnings for GCC 6.xMasahiro Yamada2016-10-18-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Marek reports warnings in UniPhier pinctrl drivers when compiled by GCC 6.x, like: drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c:58:18: warning: 'usb3_muxvals' defined but not used [-Wunused-const-variable=] static const int usb3_muxvals[] = {0, 0}; ^~~~~~~~~~~~ My intention here is to compile minimum set of pin data for SPL to save memory footprint, but GCC these days is clever enough to notice unused data arrays. We can fix it by sprinkling around __maybe_unused on those arrays, but I did not do that because they are counterparts of the pinctrl drivers in Linux. All the pin data were just copy-pasted from Linux and are kept in sync for maintainability. I chose a bit tricky way to fix the issue; calculate ARRAY_SIZE of *_pins and *_muxvals and set their sum to an unused struct member. This trick will satisfy GCC because the data arrays are used anyway, but such data arrays will be dropped from the final binary because the pointers to them are not used. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by: Marek Vasut <marex@denx.de>
* libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass2016-10-13-1/+1
| | | | | | | | | | | The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
* libfdt: Bring in upstream stringlist functionsSimon Glass2016-10-13-12/+11
| | | | | | | | | | | | | | These have now landed upstream. The naming is different and in one case the function signature has changed. Update the code to match. This applies the following upstream commits by Thierry Reding <treding@nvidia.com> : 604e61e fdt: Add functions to retrieve strings 8702bd1 fdt: Add a function to get the index of a string 2218387 fdt: Add a function to count strings Signed-off-by: Simon Glass <sjg@chromium.org>
* pinctrl: imx: do not announce driver initializationStefan Agner2016-10-07-1/+1
| | | | | | | | It is not usual that drivers announce when they have been initialized. use dev_dbg to announce device initialization. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: imx6: support i.MX6ULLPeng Fan2016-10-04-0/+5
| | | | | | | | | There two iomuxc for i.MX6ULL. one iomuxc is compatible is i.MX6UL, the other iomuxc is for SVNS usage, similar with the one in mx7. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Simon Glass <sjg@chromium.org>
* pinctrl: add driver for rk3399Kever Yang2016-09-22-0/+449
| | | | | | | This patch add pinctrl driver for rk3399. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* pinctrl: uniphier: add UniPhier sLD3 pinctrl driverMasahiro Yamada2016-09-18-0/+135
| | | | | | Add pin-mux support for UniPhier sLD3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: support 4bit-width pin-mux register capabilityMasahiro Yamada2016-09-18-14/+11
| | | | | | | On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: move register base macros from header to .c fileMasahiro Yamada2016-09-14-4/+4
| | | | | | | These macros are only referenced in pinctrl-uniphier-core.c, so they need not reside in a header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add System Bus pin-mux settingsMasahiro Yamada2016-09-14-0/+147
| | | | | | This is needed to get access to UniPhier System Bus (external bus). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: add driver for meson-gxbb pin controllerBeniamino Galvani2016-09-06-0/+704
| | | | | | | Add a pin controller driver for Meson GXBB adapted from Linux kernel. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: generic: scan for "pins" and "groups" properties in sub-nodesBeniamino Galvani2016-09-06-2/+4
| | | | | | | | | | | | | | | | | | | In cases where the pins and groups definitions are in a sub-node, as: uart_a { mux { groups = "uart_tx_a", "uart_rx_a"; function = "uart_a"; }; }; pinctrl_generic_set_state_subnode() returns an error for the top-level node and pinctrl_generic_set_state() fails. Instead, return success so that the child nodes are tried. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: fix typos in comment blocks of pinconfig_post_bind()Masahiro Yamada2016-08-20-2/+2
| | | | | | '-' is never used in function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: at91-pio4: Add pinctrl driverWenyou Yang2016-08-15-0/+190
| | | | | | | | | | | | | | AT91 PIO4 controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. The pin configuration is performed on specific registers which are shared along with the gpio controller. So regard the pinctrl device as a child of atmel_pio4 device. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* rockchip: rk3288: Fix pinctrl for GPIO bank 0John Keeping2016-07-31-2/+19
| | | | | | | | | | | | | | | | Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the register is reserved. Take the same approach as the Linux driver to update the value via read-modify-write but setting the mask for only the bits that have changed. The PMU registers ignore the top 16 bits so this works for both GRF and PMU iomux registers. Signed-off-by: John Keeping <john@metanate.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-27-24/+5
| | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-27-7/+3
| | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: sort socs according to numbersHeiko Stübner2016-07-25-9/+9
| | | | | | | | | | Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3036: pinctrl: fix config symbol namingHeiko Stübner2016-07-25-2/+2
| | | | | | | | | Rockchip socs are always named rkxxxx in all places, as also shown by the naming of the rk3036 pinctrl file itself. Therefore also name the config symbol according to this scheme. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3288: pinctrl: fix config symbol namingHeiko Stübner2016-07-25-4/+4
| | | | | | | | The rk3288 pinctrl is very specific to this soc, so should not hog the generic rockchip naming. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-30/+17
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* rockchip: pinctrl: Update the rk3288 driver to support of-platdataSimon Glass2016-07-14-1/+7
| | | | | | | | Add support for of-platdata with rk3288. This requires disabling access to the device tree and renaming the driver to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
* pinctrl: uniphier: add Ethernet pin-mux settingsMasahiro Yamada2016-07-02-0/+94
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: avoid building unneeded pin-mux tables for SPLMasahiro Yamada2016-07-02-171/+192
| | | | | | | SPL does not use all of the devices, so we can save some memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: support pin configuration for dedicated pinsMasahiro Yamada2016-07-02-154/+149
| | | | | | | | | | | | | | PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. [ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: split pinctrl driver for PH1-LD11 and PH1-LD20Masahiro Yamada2016-07-02-8/+118
| | | | | | | | | | | PH1-LD11 and PH1-LD20 have much pin controlling in common, so I added a single driver shared between them in the initial commit. However, the Ethernet pin-mux settings I am going to add are different with each other, and they may diverge more as the progress of development. Split it into two dedicated drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: allow to have pinctrl node under syscon nodeMasahiro Yamada2016-07-02-12/+12
| | | | | | | | | | | Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. This commit allows to migrate to the new DT structure. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: remove unneeded pin group nand_cs1Masahiro Yamada2016-06-30-3/+0
| | | | | | | This SoC does not support NAND CS1. This place-holder is no longer necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: fix NAND pin-mux setting for PH1-LD11/LD20Masahiro Yamada2016-06-30-2/+2
| | | | | | My mistake in the initial support patch. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: remove wrong pin-mux functions for ProXstream2Masahiro Yamada2016-06-30-2/+0
| | | | | | These are pin group names, not function names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge http://git.denx.de/u-boot-samsungTom Rini2016-06-06-0/+360
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
| * pinctrl: Add pinctrl driver support for Exynos7420 SoCThomas Abraham2016-05-25-0/+359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl driver support for Samsung's Exynos7420 SoC. The changes have been split into Exynos7420 specific and common Exynos specific portions so that this implementation is reusable on other Exynos SoCs as well. The Exynos pinctrl driver supports only device tree based pin configuration. The bindings used are similar to the ones used in the linux kernel. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * pinctrl: add the DM_UC_FLAG_SEQ_ALIAS flag for numbering the devicesThomas Abraham2016-05-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | It is possible to have multiple pin controllers in the system. Use the DM_UC_FLAG_SEQ_ALIAS flag so that the pinctrl instances are assigned a sequence number. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | rockchip: rk3288: pinctrl: support more pinsSjoerd Simons2016-05-27-1/+1
|/ | | | | | | | | The rgmii_pins node in rk3288.dtsi configures 15 pins. Increase the size of the cell array to accomedate that, otherwise only the first 10 get configured. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros qca953x.Wills Wang2016-05-21-0/+166
| | | | | | | | | This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Simon Glass <sjg@chromium.org> [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* drivers: pinctrl: Add simple pinctrl driver for Qualcomm/Atheros ar933x.Wills Wang2016-05-21-0/+151
| | | | | | | | | This is a simple pinctrl driver, it just support uart and spi pin-mux now. Signed-off-by: Wills Wang <wills.wang@live.com> Reviewed-by: Simon Glass <sjg@chromium.org> [fixed typo in commit subject line] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20Masahiro Yamada2016-04-24-4/+4
| | | | | | | I found many mistakes in the initial version. Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: rename function/array namesMasahiro Yamada2016-04-24-102/+102
| | | | | | Make function/array names match the file names for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: support UniPhier PH1-LD11 pinctrl driverMasahiro Yamada2016-04-01-6/+7
| | | | | | | | The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20 (as far as used in boot-loader), so this commit makes the driver shared between the two SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driverMasahiro Yamada2016-04-01-0/+120
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: support per-pin input enable for new SoCsMasahiro Yamada2016-04-01-1/+28
| | | | | | | | Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit prepares the core part for that. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: introduce capability flagMasahiro Yamada2016-04-01-27/+29
| | | | | | | | | | | | | | | | | | | | | The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-6/+3
| | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: drop PH1- prefix from CONFIG options and file namesMasahiro Yamada2016-03-24-19/+19
| | | | | | | | The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too long. It would not hurt to drop "PH1_" because "UNIPHIER_" already well specifies the SoC family. Also, rename files for consistency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: guard uniphier directory with CONFIG_PINCTRL_UNIPHIERMasahiro Yamada2016-03-09-9/+9
| | | | | | | | | | CONFIG_PINCTRL_UNIPHIER is more suitable than CONFIG_ARCH_UNIPHIER to guard the drivers/pinctrl/uniphier directory. The current CONFIG_PINCTRL_UNIPHIER_CORE is a bit long, so rename it into CONFIG_PINCTRL_UNIPHIER. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: set input-enable before pin-muxingMasahiro Yamada2016-03-09-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. [ ported from Linux commit bac7f4c1bf5e7c6ccd5bb71edc015b26c77f7460 ] Fixes: 5dc626f83619 ("pinctrl: uniphier: add UniPhier pinctrl core support") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: imx: Support i.MX7DPeng Fan2016-02-21-0/+56
| | | | | | | | | | | Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: imx: Introduce pinctrl driver for i.MX6Peng Fan2016-02-21-0/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: pinctrl: Add pinctrl driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+374
| | | | | | | | | | | | | | In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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