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* pinctrl: imx: Support i.MX7DPeng Fan2016-02-21-0/+56
| | | | | | | | | | | Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: imx: Introduce pinctrl driver for i.MX6Peng Fan2016-02-21-0/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: pinctrl: Add pinctrl driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+374
| | | | | | | | | | | | | | In PIC32 pin-controller is a combined gpio-controller, pin-mux and pin-config module. Remappable peripherals are assigned pins through per-pin based muxing logic. And pin configuration are performed on specific port registers which are shared along with gpio controller. Note, non-remappable peripherals have default pins assigned thus require no muxing. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* bug.h: move BUILD_BUG_* defines to include/linux/bug.hMasahiro Yamada2016-01-25-3/+1
| | | | | | | | | | | | | | | | BUILD_BUG_* macros have been defined in several headers. It would be nice to collect them in include/linux/bug.h like Linux. This commit is cherry-picking useful macros from include/linux/bug.h of Linux 4.4. I did not import BUILD_BUG_ON_MSG() because it would not work if it is used with include/common.h in U-Boot. I'd like to postpone it until the root cause (the "error()" macro in include/common.h causes the name conflict with "__attribute__((error()))") is fixed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* rockchip: rk3288: pinctrl: Fix HDMI pinctrlSimon Glass2016-01-21-0/+2
| | | | | | | Since the device tree does not specify the EDID pinctrl option for HDMI we must set it manually. Fix the driver to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Implement the get_gpio_mux() methodSimon Glass2016-01-21-16/+52
| | | | | | | Implement this so that the GPIO command will be able to report whether a GPIO is used for input or output. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Reduce the size for SPLSimon Glass2016-01-21-3/+17
| | | | | | | This file has many features that are not needed by SPL. Use #ifdef to remove the unused features and reduce the code size. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pinctrl: Add a way for a GPIO driver to obtain a pin functionSimon Glass2016-01-21-0/+10
| | | | | | | | | | | | | GPIO drivers want to be able to show if a pin is enabled for input, output, or is being used by another function. Some drivers can easily find this and the code is included in the driver. For some SoCs this is more complex. Conceptually this should be handled by pinctrl rather than GPIO. Most pinctrl drivers will have this feature anyway. Add a method by which a GPIO driver can obtain the pin mux value given a GPIO reference. This avoids repeating the code in two places. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: pinctrl: Add a full pinctrl driverSimon Glass2016-01-21-1/+229
| | | | | | | We can make use of the device tree to configure pinctrl settings. Add this support for the driver so we can use it in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-21-2/+2
| | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pinctrl: Add a function to parse PIN_CONFIG flagsSimon Glass2016-01-21-0/+12
| | | | | | | | Add a function which produces a flags word from a few common PIN_CONFIG settings. This is useful for simple pinctrl drivers that don't need to worry about drive strength, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Bind GPIO banksJeffy Chen2016-01-21-0/+8
| | | | | | | | Call dm_scan_fdt_node() in rk3036 pinctrl uclass binding. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* pinctrl: Avoid binding all pinconfig nodes before relocationSimon Glass2016-01-20-0/+4
| | | | | | | | This can create a large number of pinctrl devices. It chews up early malloc() memory and takes time. Only bind those which are marked as needed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3036: Add pinctrl driverhuang lin2015-12-01-0/+286
| | | | | | | Add a driver which support pin multiplexing setup for rk3036 Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* Various Makefiles: Add SPDX-License-Identifier tagsTom Rini2015-11-10-0/+8
| | | | | | | | | | | After consulting with some of the SPDX team, the conclusion is that Makefiles are worth adding SPDX-License-Identifier tags too, and most of ours have one. This adds tags to ones that lack them and converts a few that had full (or in one case, very partial) license blobs into the equivalent tag. Cc: Kate Stewart <kstewart@linuxfoundation.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*Masahiro Yamada2015-09-25-6/+6
| | | | | | | I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD6b pinctrl driverMasahiro Yamada2015-09-25-0/+140
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD6b SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier ProXstream2 pinctrl driverMasahiro Yamada2015-09-25-0/+147
| | | | | | | Add pin configuration and pinmux support for UniPhier ProXstream2 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro5 pinctrl driverMasahiro Yamada2015-09-25-0/+151
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-sLD8 pinctrl driverMasahiro Yamada2015-09-25-0/+148
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-sLD8 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-Pro4 pinctrl driverMasahiro Yamada2015-09-25-0/+137
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-Pro4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier PH1-LD4 pinctrl driverMasahiro Yamada2015-09-25-0/+141
| | | | | | Add pin configuration and pinmux support for UniPhier PH1-LD4 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* pinctrl: uniphier: add UniPhier pinctrl core supportMasahiro Yamada2015-09-23-0/+278
| | | | | | | The core support for the pinctrl drivers for all the UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pinctrl: move dm_scan_fdt_node() out of pinctrl uclassMasahiro Yamada2015-09-19-6/+17
| | | | | | | | | | | | | | | | | | | | | Commit c5acf4a2b3c6 ("pinctrl: Add the concept of peripheral IDs") added some additional change that was not mentioned in the git-log. That commit added dm_scan_fdt_node() in the pinctrl uclass binding. It should be handled by the simple-bus driver or the low-level driver, not by the pinctrl framework. I guess Simon's motivation was to bind GPIO banks located under the Rockchip pinctrl device. It is true some chips have sub-devices under their pinctrl devices, but it is basically SoC-specific matter. This commit partly reverts commit c5acf4a2b3c6 to keep the only pinctrl-generic features in the uclass. The dm_scan_fdt_node() should be called from the rk3288_pinctrl driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: Add pinctrl driverSimon Glass2015-09-02-0/+459
| | | | | | | Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>
* pinctrl: Add the concept of peripheral IDsSimon Glass2015-09-02-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model. Masahiro's new simple pinctrl gets around this by providing a set_state_simple() pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally. However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock. There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing set_state_simple() is effectively the union of these. Signed-off-by: Simon Glass <sjg@chromium.org>
* pinctrl: Add help text to KconfigSimon Glass2015-09-02-1/+10
| | | | | | | The pinctrl Kconfig options should have help messages. Add this to a few options. Signed-off-by: Simon Glass <sjg@chromium.org>
* pinctrl: sandbox: add sandbox pinctrl driverMasahiro Yamada2015-08-31-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver actually does nothing but test pinctrl uclass, and demonstrate how things work. To try this driver, uncomment /* #define DEBUG */ in the drivers/pinctrl/pinctrl-sandbox.c, and debug messages will be displayed. DRAM: 128 MiB sandbox pinmux: group = 1 (serial_a), function = 1 (serial) Using default environment In: cros-ec-keyb Out: lcd Err: lcd Net: Net Initialization Skipped eth0: eth@10002000, eth1: eth@80000000, eth5: eth@90000000 => i2c dev 0 Setting bus to 0 sandbox pinmux: group = 0 (i2c), function = 0 (i2c) sandbox pinconf: group = 0 (i2c), param = 3, arg = 1 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* pinctrl: add pin control uclass supportMasahiro Yamada2015-08-31-0/+702
This creates a new framework for handling of pin control devices, i.e. devices that control different aspects of package pins. This uclass handles pinmuxing and pin configuration; pinmuxing controls switching among silicon blocks that share certain physical pins, pin configuration handles electronic properties such as pin- biasing, load capacitance etc. This framework can support the same device tree bindings, but if you do not need full interface support, you can disable some features to reduce memory foot print. Typically around 1.5KB is necessary to include full-featured uclass support on ARM board (CONFIG_PINCTRL + CONFIG_PINCTRL_FULL + CONFIG_PINCTRL_GENERIC + CONFIG_PINCTRL_PINMUX), for example. We are often limited on code size for SPL. Besides, we still have many boards that do not support device tree configuration. The full pinctrl, which requires OF_CONTROL, does not make sense for those boards. So, this framework also has a Do-It-Yourself (let's say simple pinctrl) interface. With CONFIG_PINCTRL_FULL disabled, the uclass itself provides no systematic mechanism for identifying the peripheral device, applying pinctrl settings, etc. They must be done in each low-level driver. In return, you can save much memory footprint and it might be useful especially for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-10-31 13:24:34 +0000