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* ppc4xx: Fix sending type 1 PCI transactionsFelix Radensky2010-01-23-1/+2
| | | | | | | | | | The list of 4xx SoCs that should send type 1 PCI transactions is not defined correctly. As a result PCI-PCI bridges and devices behind them are not identified. The following 4xx variants should send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc/8xxx: Remove is_fsl_pci_agentKumar Gala2010-01-05-0/+9
| | | | | | | | All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent that uses the standard PCI programming model to determine host vs agent/end-point. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci_init_port end-point initialization is brokenEd Swarthout2009-11-04-1/+17
| | | | | | | | | | | | | commit 70ed869e broke fsl pcie end-point initialization. Returning 0 is not correct. The function must return the first free bus number for the next controller. fsl_pci_init() must still be called and a bus allocated even if the controller is an end-point. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Revert "ppc/85xx/pci: fsl_pci_init: pcie agent mode support"Kumar Gala2009-11-04-16/+2
| | | | | | | | | | | This reverts commit 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc. There isn't any need to modify the API for fsl_pci_init_port to pass the status of host/agent(end-point) status. We can determine that internally to fsl_pci_init_port. Revert the patch that makes the API change. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/pci: fsl_pci_init: pcie agent mode supportVivek Mahajan2009-10-27-2/+16
| | | | | | | | | | | | | | | Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up p1_p2_rdb PCI setupKumar Gala2009-09-24-1/+1
| | | | | | | | General code cleanup to use in/out IO accessors as well as making the code that prints out info sane between board and generic fsl pci code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controllerPoonam Aggrwal2009-08-28-0/+44
| | | | | | | | | fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memoryKumar Gala2009-08-28-63/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala2009-08-28-19/+13
| | | | | | | | Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-1/+7
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-2/+4
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: Add esd VME8349 board supportReinhard Arlt2009-07-27-1/+1
| | | | | | | | | | This patch adds support for the esd VME8349 board equipped with the MPC8349. It's a VME PMC carrier board equipped with the Tundra TSI148 VME-bridge. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]xPeter Tyser2009-06-12-1/+1
| | | | | | | | Use the standard lowercase "x" capitalization that other Freescale architectures use for CPU defines to prevent confusion and errors Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-04-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* sh: Add some register value configurable to PCI of SH7780Yoshihiro Shimoda2009-03-12-3/+3
| | | | | | | | Some register value was hardcoded for System memory size 128MB and memory offset 0x08000000. This patch fixed the problem. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: Add system memory registration to PCI for SH4Yoshihiro Shimoda2009-03-12-0/+10
| | | | | | | It is necessary for some pci device driver. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* PCI: Add pci_last_busno() helperAnton Vorontsov2009-02-23-0/+13
| | | | | | | | | | This is just a handy routine that reports last PCI busno: we walk down all the hoses and return last hose's last_busno. Will be used by PCI/PCIe initialization code. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* drivers/pci: Create pci_map_bar functionBecky Bruce2009-02-10-0/+19
| | | | | | | | It is no longer always true that the pci bus address can be used as the virtual address for pci accesses. pci_map_bar() is created to return the virtual address for a pci region. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* pci: give preference to non-PCI_REGION_SYS_MEMORY regions when matchingKumar Gala2009-02-07-24/+78
| | | | | | | | | | When we search for an address match in pci_hose_{phys_to_bus,bus_to_phys} we should give preference to memory regions that aren't system memory. Its possible that we have over mapped system memory in the regions and we want to avoid depending on the order of the regions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-7/+7
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ixp: move pci drivers to drivers/pciJean-Christophe PLAGNIOL-VILLARD2009-01-31-0/+572
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* pci/fsl_pci_init: Enable inbound PCI config cyclesPeter Tyser2008-12-19-0/+29
| | | | | | | | Add fsl_pci_config_unlock() function to enable a PCI/PCIe interface configured in agent/endpoint mode to respond to inbound PCI configuration cycles. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* sh: r2dplus fix register accessJean-Christophe PLAGNIOL-VILLARD2008-12-10-2/+2
| | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* drivers/fsl_pci_init: Fix compile warningKumar Gala2008-12-09-0/+2
| | | | | | | | | fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows': fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type The check only makes sense if we are CONFIG_PHYS_64BIT Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/fsl_pci_init: Fix inbound window mapping bugBecky Bruce2008-12-03-1/+1
| | | | | | | | | | | | | The current code will cause the creation of a 4GB window starting at 0 if we have more than 4GB of RAM installed, which overlaps with PCI_MEM space and causes pci_bus_to_phys() to return erroneous information. Limit the size to 4GB - 1; which causes the code to create one 2GB and one 1GB window instead. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* powerpc: fix pci window initialization to work with > 4GB DRAMBecky Bruce2008-10-27-3/+7
| | | | | | | | | The existing code has a few errors that need to be fixed in order to support large RAM sizes. Fix those, and add a comment to make it clearer. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Removed a bunch pointless trailing backslashes.Kumar Gala2008-10-27-7/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Added fdt helper for setting up bus-ranges & dma-rangesKumar Gala2008-10-24-0/+20
| | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* pci/fsl_pci_init: Add a common PCI inbound setup functionKumar Gala2008-10-24-0/+81
| | | | | | | | Add a common setup function that determines the pci_region(s) based on how much memory we have in the system. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* pci/fsl_pci_init: Enable larger address and setting inbound windows properlyKumar Gala2008-10-24-14/+24
| | | | | | | | | | | | | | | | * PCI Inbound window was setup incorrectly. The PCI address and system address were swapped. The PCI address should be setting piwar/piwbear and the system address should be setting pitar. * Removed masking of addresses to allow for system address to support system address & PCI address >32-bits * Set PIWBEAR & POTEAR to allow for full 64-bit PCI addresses * Respect the PCI_REGION_PREFETCH for inbound windows Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* pci: Allow for PCI addresses to be 64-bitKumar Gala2008-10-24-47/+78
| | | | | | | | | | PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-26/+26
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* fsl_pci_init do not scan bus when configured as an end-pointEd Swarthout2008-10-13-2/+15
| | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* sh: Fix compile warningNobuhiro Iwamatsu2008-09-19-17/+22
| | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* drivers/pci: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-28/+4
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* pci: sh: Add pci_skip_dev and pci_print_dev functionNobuhiro Iwamatsu2008-07-15-0/+12
| | | | | | | Add function of new PCI, pci_skip_dev and pci_print_dev. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Code cleanup: fix old style assignment ambiguities like "=-" etc.Wolfgang Denk2008-07-14-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* pci: Move PCI device configuration check into a separate weak functionStefan Roese2008-07-10-24/+46
| | | | | | | | | | | This patch moves the check, if a device should be skipped in PCI PNP configuration into the function pci_skip_dev(). This function is defined as weak so that it can be overwritten by a platform specific one if needed. The check if the device should get printed in the PCI summary upon bootup (when CONFIG_PCI_SCAN_SHOW is defined) is moved to the function pci_print_dev() which is also defined as weak too. Signed-off-by: Stefan Roese <sr@denx.de>
* Convert mpc7448hpc2 to CONFIG_OF_LIBFDTGerald Van Baren2008-06-09-14/+19
| | | | | | | | | | | | | This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: This conversion is untested because I do not have a board to test it on. NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) /aliases/ethernet1 property for the ethernet to work. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-22/+22
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Revert "pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config option"Wolfgang Denk2008-05-12-10/+3
| | | | | This reverts commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 which broke many PowerPC boards.
* Update pci code to use phys_addr_tBecky Bruce2008-05-10-4/+4
| | | | | | | | Physical addrs need to be represented by phys_addr_t, not unsigned long. Otherwise, systems that use CONFIG_PHYS_64BIT are going to fail mightily. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* fsl_pci: Only modify registers if we have themKumar Gala2008-04-24-1/+2
| | | | | | pme_msg_det exists only on PCIe controllers only set it if we are a "bridge". Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boardsTsiChung Liew2008-04-13-1/+1
| | | | | | | Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* sh: Add support PCI host driver for SH7751/SH7751RNobuhiro Iwamatsu2008-03-28-0/+200
| | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* sh: Move SuperH PCI driver from cpu/sh4 to drivers/pciNobuhiro Iwamatsu2008-03-28-0/+185
| | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pci: Add CONFIG_PCI_SKIP_HOST_BRIDGE config optionNobuhiro Iwamatsu2008-03-23-3/+10
| | | | | | | | | | | | In current source code, when the device number of PCI is 0, process PCI bridge without fail. However, when the device number is 0, it is not PCI always bridge. There are times when device of PCI allocates. When CONFIG_PCI_SKIP_HOST_BRIDGE is enable, this problem is solved when use this patch. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Acked-by: Stefan Roese <sr@denx.de>
* Handle MPC85xx PCIe reset errata (PCI-Ex 38)Kumar Gala2007-12-11-0/+23
| | | | | | | On the MPC85xx boards that have PCIe enable the PCIe errata fix. (MPC8544DS, MPC8548CDS, MPC8568MDS). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* drivers/pci : move pci drivers to drivers/pciJean-Christophe PLAGNIOL-VILLARD2007-11-24-0/+1711
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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