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path: root/drivers/pci
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* dm: core: Replace of_offset with accessorSimon Glass2017-02-08-7/+8
| | | | | | | | | At present devices use a simple integer offset to record the device tree node associated with the device. In preparation for supporting a live device tree, which uses a node pointer instead, refactor existing code to access this field through an inline function. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Don't try to run the VGA BIOS in 64-bit modeSimon Glass2017-02-06-1/+1
| | | | | | | This is not supported, so disable it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: mvebu: Fix Armada 38x supportDirk Eibach2017-02-01-12/+13
| | | | | | | | | | | | Armada 38x has four PCI ports, not three. The optimization in pci_init_board() seems to assume that every port has three lanes. This is obviously wrong, and breaks support for Armada 38x. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-01-25-0/+7
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| * mpc85xx: pcie: Implement workaround for Erratum A007815Tony O'Brien2017-01-24-0/+7
| | | | | | | | | | | | | | | | | | | | | | The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | Drop CONFIG_WINBOND_83C553Simon Glass2017-01-25-207/+0
|/ | | | | | This is not used in U-Boot. Drop this option and associated dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
* kconfig: move FSL_PCIE_COMPAT to platform KconfigHou Zhiqiang2017-01-18-4/+4
| | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: remove unnecessary legacy codeMinghuan Lian2017-01-18-716/+1
| | | | | | | | | | All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: add pci driver based on DMMinghuan Lian2017-01-18-0/+754
| | | | | | | | | | | | | There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: layerscape: move kernel DT fixup to a separate fileHou Zhiqiang2017-01-18-311/+343
| | | | | | | | | To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: remove pci_bus_to_hose(0) callingMinghuan Lian2017-01-18-10/+7
| | | | | | | | | | | | | | There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* dm: pci: return the real controller in pci_bus_to_hose()Minghuan Lian2017-01-18-1/+1
| | | | | | | | | | | | | for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: kconfig: fix spelling in descriptionMarcel Ziswiler2017-01-03-1/+1
| | | | | | | Fix 'driver model' rather than 'driver mode' in description. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: mvebu: Add PCIe driver for Armada-8KShadi Ammouri2016-12-05-0/+546
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for the PCIe controller integrated in the Marvell Armada-8K SoC. This controller is based on the DesignWare IP core. The original version was written by Shadi and Yehuda. I ported this driver to the latest mainline U-Boot version with DM support. Tested on the Marvell DB-88F8040 Armada-8K eval board. Signed-off-by: Shadi Ammouri <shadi@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
* pci: sh7751: map PCI memory space into SDRAMVladimir Zapolskiy2016-12-02-6/+4
| | | | | | | | | | | | | For ease of use and accounting a condition that on SH4 pci_phys_to_bus() and pci_bus_to_phys() are one in one mappings due to unimplemented __iomem() conversion, this change fixes access to SDRAM memory by PCI devices. This change also generalizes PCI system memory configuration, which is taken from board specific defines rather than hardcoded in the PCI host driver. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* pci: sh7751: fix up PCI I/O space addressVladimir Zapolskiy2016-12-02-1/+1
| | | | | | | | | | | | The change actually maps PCI I/O window to the same address on PCI bus as it is stated by a comment, before the change transfers to the PCI I/O space are failed due to misconfiguration of the most significant 14 bits of the PCI address in PCIIOBR (note that it is set to 0x0). Most probably the problem remained unnoticed, because communcation to all tested PCI devices is done over PCI memory space only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* pci: Move CONFIG_PCI_PNP to KconfigBin Meng2016-10-28-0/+7
| | | | | | | | | | Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers/pci/Kconfig: Add PCITom Rini2016-10-27-2/+10
| | | | | | | Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* libfdt: Sync fdt_for_each_subnode() with upstreamSimon Glass2016-10-13-1/+1
| | | | | | | | | | | The signature for this macro has changed. Bring in the upstream version and adjust U-Boot's usages to suit. Signed-off-by: Simon Glass <sjg@chromium.org> Update to drivers/power/pmic/palmas.c: Signed-off-by: Keerthy <j-keerthy@ti.com> Change-Id: I6cc9021339bfe686f9df21d61a1095ca2b3776e8
* vbe: Make vbe_setup_video_priv() publicBin Meng2016-10-12-3/+3
| | | | | | | vbe_setup_video_priv() might be useful to other drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: video: Output verbose information in vbe_setup_video()Bin Meng2016-10-12-1/+8
| | | | | | | | With DM conversion, information like "Video: 1024x768x16" is not shown anymore. Now add these verbose output back. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: video: Add driver-model support to vesa graphicsSimon Glass2016-10-11-0/+55
| | | | | | | | | | Provide a function to run the Vesa BIOS for a given PCI device and obtain the resulting configuration (e.g. display size) for use by the video uclass. This makes it easier to write a video driver that uses vesa and supports driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* pci: Flip condition for detecting non-PCI parent devicesPaul Burton2016-09-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In pci_uclass_pre_probe an attempt is made to detect whether the parent of a device is a PCI device and that the device is thus a bridge. This was being done by checking whether the parent of the device is of the UCLASS_ROOT class. This causes problems if the PCI controller is a child of some other non-PCI node, for example a simple-bus node. For example, if the device tree contains something like the following then pci_uclass_pre_probe would incorrectly believe that the PCI controller is a bridge, with a PCI parent: / { some_child { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <>; pci_controller: pci@10000000 { compatible = "my-pci-controller"; device_type = "pci"; reg = <0x10000000 0x2000000>; }; }; }; Avoid this incorrect detection of bridges by instead checking whether the parent devices class is UCLASS_PCI and treating a device as a bridge when this is true, making use of device_is_on_pci_bus to perform this test. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: xilinx: Add a driver for Xilinx AXI to PCIe bridgePaul Burton2016-09-21-0/+228
| | | | | | | | | | This patch adds a driver for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. This is mostly a case of implementing PCIe ECAM specification, but with some quirks about what devices are valid to access. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: tegra: port to standard clock/reset/pwr domain APIsStephen Warren2016-08-15-5/+159
| | | | | | | | | | | | | Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-07-28-1/+5
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| * pci: allow disabling of pci init/enum via envTim Harvey2016-07-28-0/+4
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * pcie_imx: increment timeout for link upStefano Babic2016-07-12-1/+1
| | | | | | | | | | | | | | On some boards, the current 20ms timeout is hit. Increase it to 40mS. Signed-off-by: Stefano Babic <sbabic@denx.de>
* | dm: Use dm_scan_fdt_dev() directly where possibleSimon Glass2016-07-27-21/+4
| | | | | | | | | | | | | | Quite a few places have a bind() method which just calls dm_scan_fdt_dev(). We may as well call dm_scan_fdt_dev() directly. Update the code to do this. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()Simon Glass2016-07-27-12/+2
| | | | | | | | | | | | | | This new function is more convenient for callers, and handles pre-relocation situations automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | pci: Add board_ prefix to should_load_oprom() and make it weakBin Meng2016-07-12-2/+2
| | | | | | | | | | | | | | | | | | For consistency with board_should_run_oprom(), do the same to should_load_oprom(). Board support codes can provide this one to override the default weak one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: Make load_oprom and run_oprom independentBin Meng2016-07-12-4/+1
| | | | | | | | | | | | | | | | | | At present should_load_oprom() calls board_should_run_oprom() to determine whether oprom should be loaded. But sometimes we just want to load oprom without running. Make them independent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | pci: Remove CONFIG_ALWAYS_LOAD_OPROMBin Meng2016-07-12-2/+0
|/ | | | | | | This option is defined at nowhere. Remove it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: tegra: actually program REFCLK_CFG* on recent SoCsStephen Warren2016-07-05-9/+10
| | | | | | | | | | | | | | | On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However, part of tegra_pcie_phy_enable() needs to happen in all cases. Move that code to tegra_pcie_port_enable() instead. For reference, NVIDIA's downstream Linux kernel performs this operation in tegra_pcie_enable_rp_features(), which is called immediately after tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot driver, we'll just add it to the tail of tegra_pcie_port_enable() instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: tegra: correctly program PADS_REFCLK registersStephen Warren2016-07-05-13/+9
| | | | | | | | | | | | | | | | The value that should be programmed into the PADS_REFCLK register varies per SoC. Fix the Tegra PCIe driver to program the correct values. Future SoCs will require different values in cfg0/1, so the two values are stored separately in the per-SoC data structures. For reference, the values are all documented in NV bug 1771116 comment 20. The Tegra210 value doesn't match the current TRM, but I've filed a bug to get the TRM fixed. Earlier TRMs don't document the value this register should contain, but the ASIC team has validated all these values, except for the Tegra20 value which is simply left unchanged in this patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pcie/layerscape: fix bug in bus number computation when setting msi-mapBogdan Purcareata2016-06-03-3/+6
| | | | | | | | | | | | | | | When multiple PCI cards are present in an ls2080a board, the second card does not get its msi-map set up properly due to a bug in computing the bus number. The bus number returned by PCI_BDF() is not the actual PCI bus number, but instead represents a global u-boot PCI bus number. A given bus number is relative to hose->first_busno, so that has to be subtracted from the PCI device id. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Acked-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: Drop CONFIG_SYS_SCSI_SCAN_BUS_REVERSESimon Glass2016-05-17-4/+0
| | | | | | | This option is not used by any board. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: tegra: fix DM conversion issues on Tegra20Stephen Warren2016-05-04-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra20's PCIe controller has a couple of quirks. There are workarounds in the driver for these, but they don't work after the DM conversion: 1) The PCI_CLASS value is wrong in HW. This is worked around in pci_tegra_read_config() by patching up the value read from that register. Pre-DM, the PCIe core always read this via a 16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used, so we need to check for offset 0x8 instead. Mask the offset value back to 32-bit alignment to make this work in all cases. 2) Accessing devices other than dev 1 causes a data abort. Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code called during enumeration while iterating over a bus. The DM PCIe core doesn't use this function. Instead, enhance tegra_pcie_conf_address() to validate the bdf being accessed, and refuse to access invalid devices. Since pci_skip_dev() isn't used, delete it. I've also validated that both these WARs are only needed for Tegra20, by testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in conditionally. Fixes: e81ca88451cf ("dm: tegra: pci: Convert tegra boards to driver model for PCI") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* pci: Device scanning range fixYoshinori Sato2016-04-25-1/+1
| | | | | | | | The terminal condition in the area where a PCI device is scanned is wrong, and 1f.7 isn't scanned. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci/layerscape: set LUT and msi-map for discovered PCI devicesStuart Yoder2016-03-21-0/+147
| | | | | | | | | | | | | | | | | | msi-map properties are used to tell an OS how PCI requester IDs are mapped to ARM SMMU stream IDs. for all PCI devices discovered in a system: -allocate a LUT (look-up-table) entry in that PCI controller -allocate a stream ID for the device -program and enable a LUT entry (maps PCI requester id to stream ID) -set the msi-map property on the controller reflecting the LUT mapping basic bus scanning loop/logic was taken from drivers/pci/pci.c pci_hose_scan_bus(). Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: ls2080a: remove obsolete stream ID partitioning supportStuart Yoder2016-03-21-70/+0
| | | | | | | | | | Remove stream ID partitioning support that has been made obsolete by upstream device tree bindings that specify how representing how PCI requester IDs are mapped to MSI specifiers and SMMU stream IDs. Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* pci: Correct a few comments and nitsSimon Glass2016-03-17-1/+0
| | | | | | | | Two comments are missing a parameter and there is an extra blank line. Also two of the region access macros are misnamed. Correct these problems. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add functions to update PCI configuration registersSimon Glass2016-03-17-0/+57
| | | | | | | | | It is common to read a config register value, clear and set some bits, then write back the updated value. Add functions to do this in one step, for convenience. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Break out the common region display codeSimon Glass2016-03-14-34/+17
| | | | | | | | Each region is displayed in almost the same way. Break out this common code into its own function. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-3/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Fix compiler warnings in dm_pciauto_setup_device()Bin Meng2016-02-26-1/+1
| | | | | | | | | | | | Fix the following compiler warnings when DEBUG is on. warning: 'bar_res' may be used uninitialized in this function. drivers/pci/pci_auto.c:101:21: if (!enum_only && pciauto_region_allocate(bar_res, bar_size, ^ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci_rom: fix may be used uninitialized warningAndreas Bießmann2016-02-24-1/+1
| | | | | | | | | | | | | | | | Building pci_rom.c with my toolchain complains about may be used uninitialized rom varaible: ---8<--- +drivers/pci/pci_rom.c:269:25: note: 'rom' was declared here w+drivers/pci/pci_rom.c: In function 'dm_pci_run_vga_bios': w+drivers/pci/pci_rom.c:154:14: warning: 'rom' may be used uninitialized in this function [-Wmaybe-uninitialized] --->8--- Fix this as done in 55616b86c745fcac5a791268ab8e7cba36965c0f the ram variable. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-01-29-0/+15
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| * Implement "pci enum" command for CONFIG_DM_PCIStephen Warren2016-01-28-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they are without that config option enabled. No command exists to enumerate the PCI buses. Hence, unless some board-specific code causes PCI enumeration, PCI-based Ethernet devices are not detected, and network access is not available. This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a mechanism whereby PCI can be enumerated. do_pci()'s handling of case 'e' is moved into a single location before the dev variable is assigned, in order to skip calculation of dev. The enum sub-command doesn't need the dev value, and skipping its calculation avoids an irrelevant error being printed. Using a command to initialize PCI like this has a disadvantage relative to enumerating PCI at boot. In particular, Ethernet devices are not probed during PCI enumeration, but only when used. This defers setting variables such as ethact, ethaddr, etc. until the first network-related command is executed. Hopefully this will not cause further issues. Perhaps in the long term, we need a "net start/enum" command too? Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-03 08:09:06 +0000