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path: root/drivers/pci/pci_common.c
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* dm: pci: Switch to DM API for PCI address mappingSimon Glass2016-01-12-1/+1
| | | | | | | | We should use the new address mapping functions unless we are in compatibility mode. Disable the old functions by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Drop the old version of pci_find_class()Simon Glass2016-01-12-42/+42
| | | | | | | | Move this function into the compatibility file so that it is not available by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Drop the old version of pci_find_device/s()Simon Glass2016-01-12-0/+2
| | | | | | | | Move these functions into the compatibility file so that they are not available by default. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: fix address range check in __pci_hose_phys_to_bus()Marcel Ziswiler2015-11-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The address range check may overflow if the memory region is located at the top of the 32-bit address space. This can e.g. be seen on TK1 if using the E1000 gigabit Ethernet driver where start and size are both 0x80000000 leading to the following messages: Apalis TK1 # tftpboot $loadaddr test_file Using e1000#0 device TFTP from server 192.168.10.1; our IP address is 192.168.10.2 Filename 'test_file'. Load address: 0x80408000 Loading: pci_hose_phys_to_bus: invalid physical address This patch fixes this by changing the order of the addition vs. subtraction in the range check just like already done in __pci_hose_bus_to_phys(). Reported-by: Ivan Mercier <ivan.mercier@nexvision.fr> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* pci: fix checking PCI_REGION_MEM in pci_hose_phys_to_bus()Cheng Gu2015-11-12-2/+2
| | | | | | | | | | | | | | | When converting between PCI bus and phys addresses, a two pass search was introduced with preference to non-PCI_REGION_SYS_MEMORY regions. See commit 2d43e873a29ca4959ba6a30fc7fb396d3fd0dccf. However, since PCI_REGION_MEM is defined as 0, the if statement was always asserted true: ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) This patch uses PCI_REGION_TYPE bit to check if the region is PCI_REGION_MEM: ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) Signed-off-by: Cheng Gu <chenggu@marvell.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Support bridge device configuration correctlyBin Meng2015-07-28-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-0/+6
| | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Move pci_hose_phys_to_bus() to pci_common.cBin Meng2015-06-04-4/+66
| | | | | | | | pci_hose_phys_to_bus() is needed by several drivers. Move it to pci_common.c to avoid a broken build when CONFIG_DM_PCI is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Move common PCI functions into their own fileSimon Glass2015-04-16-0/+292
Driver model will share many functions with the existing PCI implementation. Move these into their own file to avoid duplication and confusion. Signed-off-by: Simon Glass <sjg@chromium.org>