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path: root/drivers/pci/pci-uclass.c
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* dm: Use uclass_first_device_err() where it is usefulSimon Glass2016-03-14-3/+1
| | | | | | Use this new function in places where it simplifies the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* Implement "pci enum" command for CONFIG_DM_PCIStephen Warren2016-01-28-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they are without that config option enabled. No command exists to enumerate the PCI buses. Hence, unless some board-specific code causes PCI enumeration, PCI-based Ethernet devices are not detected, and network access is not available. This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a mechanism whereby PCI can be enumerated. do_pci()'s handling of case 'e' is moved into a single location before the dev variable is assigned, in order to skip calculation of dev. The enum sub-command doesn't need the dev value, and skipping its calculation avoids an irrelevant error being printed. Using a command to initialize PCI like this has a disadvantage relative to enumerating PCI at boot. In particular, Ethernet devices are not probed during PCI enumeration, but only when used. This defers setting variables such as ethact, ethaddr, etc. until the first network-related command is executed. Hopefully this will not cause further issues. Perhaps in the long term, we need a "net start/enum" command too? Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to write a BARSimon Glass2016-01-24-0/+8
| | | | | | | | Add a driver-model version of the pci_write_bar32 function so that this is supported in the new API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Move pci_bus_to_hose() to compatibilitySimon Glass2016-01-24-15/+1
| | | | | | | | This function should not be used by driver-model code, so move it to the compatibility portion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Tidy up comments in pci_bind_bus_devices()Simon Glass2016-01-12-3/+1
| | | | | | | | | The current comments are confusing. We don't actually bind a generic device when the device tree has no information. We try to scan available PCI drivers. Update the comments to reflect this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add driver model API functions for address mappingSimon Glass2016-01-12-0/+136
| | | | | | | | At present the PCI address map functions use the old API. Add new functions for this so that drivers can be converted. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to read a PCI BARSimon Glass2016-01-12-0/+13
| | | | | | | Add a driver-model function for reading the PCI BAR from a device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_class()Simon Glass2016-01-12-0/+20
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a driver-model version of pci_find_device()Simon Glass2016-01-12-0/+39
| | | | | | | | | Add a function which scans the driver model device information rather than scanning the PCI bus again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use driver model PCI API in auto-configSimon Glass2016-01-12-14/+5
| | | | | | | | | | | | | At present we are using legacy functions even in the auto-configuration code used by driver model. Add a new pci_auto.c version which uses the correct API. Create a new pci_internal.h header to hold functions that are used within the PCI subsystem, but are not exported to other drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_bus_find_bdf()Simon Glass2016-01-12-1/+1
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_bus_find_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a dm_ prefix to pci_get_bdf()Simon Glass2016-01-12-4/+5
| | | | | | | | | | | | Most driver model PCI functions have a dm_ prefix. At some point, when the old code is converted to driver model and the old functions are removed, we will drop that prefix. For consistency, we should use the dm_ prefix for all driver model functions. Update pci_get_bdf() accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to find the regions for a PCI busSimon Glass2015-12-01-0/+30
| | | | | | | | | This function looks up the controller and returns a pointer to each region type. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add a function to get the controller for a busSimon Glass2015-12-01-0/+8
| | | | | | | | | A PCI bus may be a bridge device where the controller is the bridge's parent. Add a function to return the controller device, given a PCI device. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Add functions to emulate 8- and 16-bit accessSimon Glass2015-12-01-0/+39
| | | | | | | | | Provide a few functions to support using 32-bit access to emulate 8- and 16-bit access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Support decoding ranges with duplicate entriesSimon Glass2015-12-01-3/+10
| | | | | | | | | | | | | | | | | | At present we add a new resource entry for every range entry. But some range entries refer to configuration regions. To make this work, avoid adding two regions of the same type. The later ranges will overwrite the earlier (configuration) ones. There does not seem to be a way to distinguish the configuration ranges other than by ordering (as per the device tree binding). We could perhaps instead just store one region of each type in a simple array. Once we are sure that we don't need to support multiple regions, we could change this. It would be easier to do it when all drivers are converted to use driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Set up the SDRAM mapping correctlySimon Glass2015-12-01-6/+9
| | | | | | | | | | SDRAM doesn't always start at 0. Adjust the region mapping so that it works on platforms where SDRAM is somewhere else. This needs testing on other platforms. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
* dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-21-0/+18
| | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-21-24/+1
| | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Adjust pci_find_and_bind_driver() to return -EPERMSimon Glass2015-10-21-12/+19
| | | | | | | | | | | | | | The current code returns 0 even if it failed to find or bind a driver. The caller then has to check the returned device to see if it is NULL. It is better to return an error code in this case so that it is clear what happened. Adjust the code to return -EPERM, indicating that the device was not bound because it is not needed for pre-relocation use. Add comments so that the return value is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct a few debug() statementsSimon Glass2015-10-21-2/+2
| | | | | | | | One debug() statement is missing a newline. The other has a repeated word. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Tidy up auto-config error handlingSimon Glass2015-10-21-3/+12
| | | | | | | | | | | When the auto-configuration process fails for a device (generally due to lack of memory) we should return the error correctly so that we don't continue to try memory allocations which will fail. Adjust the code to check for errors and abort if something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add an inline API to test if a device is on a PCI busBin Meng2015-09-16-2/+2
| | | | | | | | Introduce device_is_on_pci_bus() which can be utilized by driver to test if a device is on a PCI bus. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow a PCI bus to be found without an aliasSimon Glass2015-09-09-4/+24
| | | | | | | | | | | | | | At present, until a PCI bus is probed, it cannot be found by its sequence number unless it has an alias. This is the same with any device. However with PCI this is more annoying than usual, since bus 0 is always the same device. Add a function that tries a little harder to locate PCI bus 0. This means that PCI enumeration will happen automatically on the first access. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Optimize pci_uclass_post_bind()Bin Meng2015-08-26-0/+7
| | | | | | | | If there is no pci device listed in the device tree, don't bother scanning the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-26-2/+2
| | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-26-0/+21
| | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-26-11/+30
| | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-14-0/+4
| | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-14-0/+60
| | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Provide friendly config access functionsSimon Glass2015-08-14-0/+76
| | | | | | | | | At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Allow scan bridge child devices before relocationBin Meng2015-08-05-4/+0
| | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. Remove such limitation so that dm pci can be used before relocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Support bridge device configuration correctlyBin Meng2015-07-28-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Pass only device/function to pci_bus_find_devfn()Bin Meng2015-07-28-1/+1
| | | | | | | | In dm_pci_hose_probe_bus(), pci_bus_find_devfn() is called with a bdf which includes a bus number, but it really should not as this routine only expects a device/function encoding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Use complete bdf in all pci config read/write routinesBin Meng2015-07-28-27/+27
| | | | | | | | | | | | | | | | Currently pci_bus_read_config() and pci_bus_write_config() are called with bus number masked off in the parameter bdf, and bus number is supposed to be added back in the bridge driver's pci config read/write ops if the device is behind a pci bridge. However this logic only works for a pci topology where there is only one bridge off the root controller. If there is addtional bridge in the system, the logic will create a non-existent bdf where its bus number gets accumulated across bridges. To correct this, we change all pci config read/write routines to use complete bdf all the way up to the root controller. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Add a function to get the BDF for a deviceSimon Glass2015-07-21-6/+9
| | | | | | | | | It is useful to be able to find the full PCI address (bus, device and function) for a PCI device. Add a function to provide this. Adjust the existing code to use this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add support for PCI driver matchingSimon Glass2015-07-21-13/+116
| | | | | | | | | | | | | | | | | | | At present all PCI devices must be present in the device tree in order to be used. Many or most PCI devices don't require any configuration other than that which is done automatically by U-Boot. It is inefficent to add a node with nothing but a compatible string in order to get a device working. Add a mechanism whereby PCI drivers can be declared along with the device parameters they support (vendor/device/class). When no suitable driver is found in the device tree the list of such devices is consulted to determine the correct driver. If this also fails, then a generic driver is used as before. The mechanism used is very similar to that provided by Linux and the header file defintions are copied from Linux 4.1. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: x86: baytrail: Correct PCI region 3 when driver model is usedSimon Glass2015-07-14-2/+6
| | | | | | | | Commit afbbd413a fixed this for non-driver-model. Make sure that the driver model code handles this also. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-14-1/+1
| | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-14-1/+5
| | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Allow PCI bus numbering aliasesSimon Glass2015-06-04-0/+1
| | | | | | | | | | | Commit 9cc36a2 'dm: core: Add a flag to control sequence numbering' changed the default uclass behaviour to not support bus numbering. This is incorrect for PCI and that commit should have enabled the flag for PCI. Enable it so that PCI buses can be found and the 'pci' command works again. Also add a test for this. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Add a uclass for PCISimon Glass2015-04-16-0/+639
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-06 19:30:35 +0000