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* net: Add EMAC driver for H3/A83T/A64 SoCs.Amit Singh Tomar2016-07-15-0/+799
| | | | | | | | | | | This patch add EMAC driver support for H3/A83T/A64 SoCs. Tested on Pine64(A64-External PHY) and Orangepipc(H3-Internal PHY). BIG Thanks to Andre for providing some of the DT code. Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* net: rtl8169: Fix return value for rtl_send_commonOleksandr Tymoshenko2016-07-06-2/+2
| | | | | | | | | | | | | | | | | Return value of rtl_send_common propogates unmodified all the way up to eth_send and further to API consumer if CONFIG_API is enabled. Previously rtl_send_common returned number of bytes sent on success which was erroneouly detected as error condition by API consumers that checked for operation success by comparing return value with 0. Switch rtl_send_common to use common convention: return 0 on success and negative value for failure. Cc: Stephen Warren <swarren@nvidia.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* driver: net: phylib: add support for aquantia AQR106/107 PHYMingkai Hu2016-07-06-0/+28
| | | | | | | | This patch adds support for aquantia AQR106/107 PHY. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: designware: Make driver independent from DM_GPIO againAlexey Brodkin2016-07-06-3/+14
| | | | | | | | | | | | | | | | | | | | | | | Commit 90b7fc924adf "net: designware: support phy reset device-tree bindings" made DW GMAC driver dependent on DM_GPIO by unconditional usage of purely DM_GPIO stuff like: * dm_gpio_XXX() * gpio_request_by_name() But since that driver as of today might be easily used without DM_GPIO (that's the case for Synopsys AXS10x boards) we're shielding all DM_GPIO things by ifdefs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Sonic Zhang <sonic.zhang@analog.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: marvell: Do not reset 88e1310 after autonegNathan Rossi2016-06-21-4/+1
| | | | | | | | | | | | | | | | | Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
* net: phy: micrel: add support for KSZ886x switches in MIIM modeAlexey Firago2016-06-21-0/+26
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a phy driver for the Micrel KSZ886x switches. Similarly to the KSZ8895, SoC MAC is directly connected to the switch MAC on the switch CPU port, so the link to the switch is always up. KSZ886x switches can be used in the following configuration modes: - Unmanaged mode with config stored in external EEPROM - Managed mode over SPI - Managed mode over I2C - Managed mode over mdio/mdc (aka MIIM or SMI) This patch supports only unmanaged and MIIM modes. Based on Micrel KSZ886x driver from Linux kernel and Micrel KSZ8895 driver from U-Boot. Verified with the KSZ8863MLL. Signed-off-by: Alexey Firago <alexey_firago@mentor.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: rtl8169: fix switching between adaptersStephen Warren2016-06-21-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | The rtl8169 driver uses a global variable to store the register address of the adapter being operated upon. This is updated to point at the correct adapter when sending or receiving a packet, or shutting down the adapter, but not when initializing the adapter. Consequently, switching between different adapters within the same U-Boot runtime does not work correctly since the driver programs the wrong registers during rtl8169_eth_start() -> rtl8169_common_start() -> rtl8169_hw_start(). Note that since rtl8169_eth_stop() does set the global variable, the second consecutive attempt to use the "new" adapter did work even before this patch, because each time network usage is shut down, the network core calls stop, which sets the variable so that the next start does actually initialize the hardware, and the adapter works. Equally, rtl8169_eth_probe() calls rtl_init() which sets the global, so if using only a single device, or if picking the "right" device (based on probe order) when multiple devices are present, ioaddr will already be set correctly from the get-go, so the issue does not occur. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-13-76/+244
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| * net: macb: Convert to driver modelSimon Glass2016-06-12-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | Add driver-model support to this driver. The old code remains for now so that we can convert boards one at a time. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * net: macb: Flush correct cache portion when sendingSimon Glass2016-06-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | The end address of the cache flush must be cache-line-aligned since otherwise (at least on ARM926-EJS) the request is ignored. When the cache is enabled this means that packets are not sent. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * net: macb: Prepare for driver-model conversionSimon Glass2016-06-12-75/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust this driver to avoid using struct netdev in functions that driver model will call. Also refactor the receive function to be compatible with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-1/+1
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| * net: fec_mxc: use simpler runtime cpu dection macrosPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | nand: Embed mtd_info in struct nand_chipScott Wood2016-06-03-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
* | net: Add ag7xxx driver for Atheros MIPSMarek Vasut2016-05-31-0/+990
| | | | | | | | | | | | | | | | | | | | | | | | Add ethernet driver for the AR933x and AR934x Atheros MIPS machines. The driver could be easily extended to other WiSoCs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Wills Wang <wills.wang@live.com> [fixed Kconfig dependency] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | net: pcnet: Fix init on big endian 64 bitPaul Burton2016-05-31-3/+3
| | | | | | | | | | | | | | | | | | | | If dev->iobase is 64 bits wide then writing the value of the BAR into a pointer to iobase will not work on big endian systems, where the BAR value will incorrectly get written to the upper 32 bits of the 64 bit variable. Fix this by reading the BAR into a u32, matching the type expected by pci_read_config_dword. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | net: pcnet: Make 64 bit safePaul Burton2016-05-31-8/+10
| | | | | | | | | | | | | | | | Fix the pcnet driver to build safely on 64 bit platforms, in preparation for allowing MIPS64 builds for Malta boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: pcnet: Stop converting kseg1->kseg0 addressesPaul Burton2016-05-31-9/+6
| | | | | | | | | | | | | | | | Now that MIPS virt_to_phys can handle kseg1 addresses on MIPS32, stop manually converting addresses to their kseg0 equivalents in the pcnet driver. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2016-05-27-6/+80
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| * | net: designware: support phy reset device-tree bindingsSjoerd Simons2016-05-27-6/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the snps,reset-gpio, snps,reset-active-low (optional) and snps,reset-delays-us device-tree bindings. The combination of these three define how the PHY should be reset to ensure it's in a sane state. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | net: designware: fix descriptor layout and warnings on 64-bit archsBeniamino Galvani2016-05-27-29/+34
|/ / | | | | | | | | | | | | | | | | | | | | | | | | All members of the DMA descriptor must be 32-bit, even on 64-bit architectures: change the type to u32 to ensure this. Also, fix other warnings. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> [trini: Use phys_addr_t not unsigned long long to test that we're within DMA'able memory] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-25-1/+1
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| * | powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in ↵Ying Zhang2016-05-24-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | some case When using rcw protocols to support 10G on MAC9 and MAC10, these MACs should not be identified as 1G interface, otherwise, one MAC will be listed as two Ethernet ports. For example, MAC9 will be listed as FM1@TGEC1 and FM1@DTSEC9. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-530/+1158
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * | net: phy: dp83867: Add SGMII helper for configurationDan Murphy2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code assumed that if the interface is not RGMII configured then it must be SGMII configured. This device has the ability to support most of the MII interfaces. Therefore add the helper for SGMII and only configure the device if the interface is configured for SGMII. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Move is_rgmii helper to phy.hDan Murphy2016-05-24-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the phy_interface_is_rgmii to the phy.h file for all phy's to be able to use the API. This now aligns with the Linux kernel based on commit e463d88c36d42211aa72ed76d32fb8bf37820ef1 Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ti: Allow the driver to be more configurableDan Murphy2016-05-24-10/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the devicetree. If the value is not set in the devicetree then set the delay to the default. If devicetree is not used then use the default defines within the driver. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy2016-05-24-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to pass the phy-handle node offset to the phy driver. This allows the phy driver to access the DT subnode's data and parse accordingly. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: Add reading of DT phy-handle nodeDan Murphy2016-05-24-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ability to read the phy-handle node of the cpsw slave. Upon reading this handle the phy-id can be stored based on the reg node in the DT. The phy-handle also needs to be stored and passed to the phy to access any phy data that is available. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: add support for reading mac address from efuseMugunthan V N2016-05-24-17/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different TI platforms has to read with different combination to get the mac address from efuse. So add support to read mac address based on machine/device compatibles. The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c done by Tony Lindgren. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix get mdio base and gmii_sel reg from DTMugunthan V N2016-05-24-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since dra7x platforms address bus is define as 64 bits to support LAPE, fdtdec_get_addr() returns a invalid address for mdio based and gmii_sel register address. Fixing this by using fdtdec_get_addr_size_auto_noparent() which will derive address cell and size cell from its parent. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: cpsw: fix cpsw dp parse when num slaves as 1Mugunthan V N2016-05-24-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some boards number of slaves can be 1 when only one port ethernet is pinned out. So do not break when slave_index and num slaves check fails, instead continue to parse the next child. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Add PHY driver for mv88e61xx switchesKevin Smith2016-05-24-0/+1020
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: Remove unused mv88e61xx switch driverKevin Smith2016-05-24-598/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | phy: marvell: Do not reset phy after negotiationMichal Simek2016-05-24-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | phy: Wire return value from phy_config()Michal Simek2016-05-24-5/+2
| | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: phy: Handle phy_startup() error codes properlyMichal Simek2016-05-24-56/+115
| | | | | | | | | | | | | | Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | phy: Return correct error code when timeout happensMichal Simek2016-05-24-3/+3
| | | | | | | | | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-24-3/+8
|/ | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-3/+3
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* drivers: net: ldpaa: Memset pools_params as "0" before usePrabhakar Kushwaha2016-05-03-0/+1
| | | | | | | | Memset pools_params as "0" to avoid garbage value in dpni_set_pools. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-5/+5
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* armv8: LS2080A: Consolidate LS2080A and LS2085AYork Sun2016-04-06-1/+10
| | | | | | | | | | | | LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* drivers: net: vsc9953: Fix bug when PVID is shown for disabled ports onlyCodrin Ciubotariu2016-04-06-1/+1
| | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* drivers: net: vsc9953: Do not configure disabled portsCodrin Ciubotariu2016-04-06-4/+8
| | | | | | | | | | | | Some SerDes protocols might not enable all l2switch ports. In this case, these ports should not be configured to perform Rx/Tx operations. This also fixes an issue when flooded frames were also switched to disabled ports and frames start to accumulate, consuming memory and eventually causing head-of-line blocking for other frames. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-04-04-15/+255
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| * net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu2016-04-04-2/+11
| | | | | | | | | | | | | | | | | | PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: phy: Add SGMII support for TI phySiva Durga Prasad Paladugu2016-04-04-1/+38
| | | | | | | | | | | | | | | | | | Add support of SGMII to TI phy dp838367 Enable the SGMII and PCS settings in phy control, CFG2 and BIST registers Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu2016-04-04-3/+1
| | | | | | | | | | | | | | | | Return error from probe in case of invalid phy address. This fixes the issue of uboot crash if phy is not detected. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: axi_emac: Report phy-node error message permanentlyMichal Simek2016-04-04-1/+1
| | | | | | | | | | | | Do not use debug() when printing error message. Use printf instead. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit v1.1 at 2024-11-02 21:44:21 +0000