summaryrefslogtreecommitdiff
path: root/drivers/net
Commit message (Collapse)AuthorAgeLines
* net: Rename and cleanup sunxi (Allwinner) emac driverStefan Roese2014-07-06-73/+69
| | | | | | | | | | | | | | | | | There have been 3 versions of the sunxi_emac support patch during its development. Somehow version 2 ended up in upstream u-boot where as the u-boot-sunxi git repo got version 3. This bumps the version in upstream u-boot to version 3 of the patch: - Initialize MII clock earlier so mii access to allow independent use - Name change from WEMAC to EMAC to match mainline kernel & chip manual - Cosmetic code cleanup Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* armv8/fsl-lsch3: Add support to load and start MC FirmwareJ. German Rivera2014-07-03-0/+275
| | | | | | | | | | | | | | | | Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@Freescale.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-06-25-40/+101
|\
| * net: sh-eth: Fix typo from rESR_RTLF to EESR_RTLFNobuhiro Iwamatsu2014-06-10-1/+1
| | | | | | | | | | | | | | 'r' of rESR_RTLF is a mistake of E. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * net: sh-eth: Fix coding styleNobuhiro Iwamatsu2014-06-10-22/+22
| | | | | | | | | | | | | | This fixes checkpatch's warning. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * net: sh-eth: Add support R7S72100 of rmobileNobuhiro Iwamatsu2014-06-10-14/+77
| | | | | | | | | | | | | | | | | | The R7S72100 of ARM SoC that Renesas manufactured has one Ether port. This has the same IP SH-Ether. This patch adds support of the R7S72100 in SH-Ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * phy: fix create_phy_by_mask for when its given an actual search maskCormier, Jonathan2014-06-05-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask. Example usage: Replace phydev = phy_connect(bus, phy_addr, dev, phy_if) with phydev = phy_find_by_mask(bus, phy_mask, phy_if) if (phydev) phy_connect_dev(phydev, dev); Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* | net: macb: enable dcache in macbWu, Josh2014-06-14-4/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add to code to flush the dcache after we writing in DMA buffer. Also we need invalidate the dcache before we check the status in the DMA buffer. Tested in SAMA5D3x-EK with gmac0. Tftp download speed shows in below: Disable DCache: 1.1 MiB/s Enable DCache: 1.6 MiB/s Increase speed with about 40%. The code should have no impact with the boards which are not enable_dcache(). Tested in AT91SAM9M10G45EK. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | macb: make checkpatch cleanAndreas Bießmann2014-06-14-27/+29
|/ | | | | | | | This also renames the CONFIG_SYS_MACB_xx defines. They are used just local and therefore don't need the CONFIG_SYS_ prefix. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Josh Wu <josh.wu@atmel.com>
* net/designware: Make DMA burst length configurable and reduce by defaultIan Campbell2014-05-25-7/+7
| | | | | | | | | | | The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: reorder struct dw_eth_dev to pack more efficiently.Ian Campbell2014-05-25-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Thu, 2014-05-08 at 22:26 +0100, Ian Campbell wrote: > The {r,t}xbuffs fields also need to be aligned. Previously this was done > implicitly because they immediately followed the descriptor tables. Make this > explicit and also move to the head of the struct. Looks like I managed to not actually commit the move of the field to the head of the struct! v3.1 follows.... Ian. 8<------------ >From 2937ba01841887317f6792709ed57cb86b5fc0cd Mon Sep 17 00:00:00 2001 From: Ian Campbell <ijc@hellion.org.uk> Date: Thu, 1 May 2014 19:45:15 +0100 Subject: [PATCH] net/designware: reorder struct dw_eth_dev to pack more efficiently. The {tx,rx}_mac_descrtable fields are aligned to ARCH_DMA_MINALIGN, which could be 256 or even larger. That means there is a potentially huge hole in the struct before those fields, so move them to the front where they are better packed. Moving them to the front also helps ensure that so long as dw_eth_dev is properly aligned (which it is since "net/designware: ensure device private data is DMA aligned.") the {tx,rx}_mac_descrtable will be too, or at least avoids having to worry too much about compiler specifics. The {r,t}xbuffs fields also need to be aligned. Previously this was done implicitly because they immediately followed the descriptor tables. Make this explicit and also move to the head of the struct. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGNIan Campbell2014-05-25-5/+13
| | | | | | | | | | | This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: ensure device private data is DMA aligned.Ian Campbell2014-05-25-1/+2
| | | | | | | | | | struct dw_eth_dev contains fields which are accessed via DMA, so make sure it is aligned to a dma boundary. Without this I see: ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0 Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de>
* net: phy/vitesse: Add support for VSC8664 phy moduleChunhe Lan2014-05-16-0/+46
| | | | | | | | This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-0/+1
| | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/fman/memac: use default MDIO_HOLD valueShaohui Xie2014-05-13-6/+2
| | | | | | | | Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* net/designware: call phy_connect_dev() to properly setup phylib deviceIan Campbell2014-05-12-0/+2
| | | | | | | | | | | This sets up the linkage from the phydev back to the ethernet device. This symptom of not doing this which I noticed was: <NULL> Waiting for PHY auto negotiation to complete.... rather than: dwmac.1c50000 Waiting for PHY auto negotiation to complete.... Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
* net: rename and refactor eth_rand_ethaddr() functionMasahiro Yamada2014-05-12-2/+2
| | | | | | | | | | | | | | | | | | | | Some functions in include/net.h are ported from include/linux/etherdevice.h of Linux Kernel. For ex. is_zero_ether_addr() is_multicast_ether_addr() is_broadcast_ether_addr() is_valid_ether_addr(); So, we should use the same function name as that of Linux Kernel, eth_rand_addr(), for consistency. Besides, eth_rand_addr() has been implemented as an inline function. So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy: enable get_phy_id redefinableShengzhou Liu2014-05-12-1/+2
| | | | | | | | | As some PHYs have non-standard PHY ID registers, PHY Id can't be read correctly by current get_phy_id function, so we enable get_phy_id redefinable to permit specific PHY driver having own specific get_phy_id function. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* AR8035/phy: Enable autonegotiation function for ar8035Xiaobo Xie2014-05-12-3/+1
| | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* Merge branch 'u-boot/master'Albert ARIBAUD2014-05-09-866/+88
|\ | | | | | | | | | | | | Conflicts: drivers/net/Makefile (trivial merge)
| * net: zynq: Fix sparse warnings in gemMichal Simek2014-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | Add missing header. Warnings: drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static? drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: zynq: Use predefined macros instead of hardcoded valueMichal Simek2014-05-06-1/+2
| | | | | | | | | | | | MII is used by this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-04-25-8/+20
| |\
| | * ar8031: modify the config func of ar8031 to ar8021_configZhao Qiang2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3Priyanka Jain2014-04-22-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons -On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs. -On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled. So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized. Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot. This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * net/phy: Fix PHY id for VSC8514Codrin Ciubotariu2014-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | MIPS: drop incaip boardDaniel Schwierzeck2014-04-20-794/+0
| |/ | | | | | | | | | | | | | | | | This is dead hardware and no one is interested in making the necessary changes for upcoming features like generic board or driver model. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wolfgang Denk <wd@denx.de>
| * e1000: remove redundant assignmentDavid Müller (ELSOFT AG)2014-04-18-1/+0
| | | | | | | | | | Signed-off-by: David Mueller <d.mueller@elsoft.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * pcnet: force ordering of descriptor accessesPaul Burton2014-04-18-18/+19
| | | | | | | | | | | | | | | | | | | | | | The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: align rx buffers for cache invalidationPaul Burton2014-04-18-9/+12
| | | | | | | | | | | | | | | | | | | | The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * pcnet: access descriptor rings & init block uncachedPaul Burton2014-04-18-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * arm: remove lubbock board supportMasahiro Yamada2014-04-18-6/+0
| | | | | | | | | | | | | | | | | | | | | | Enough time has passed since this board was moved to Orphan. Remove. - Remove board/lubbock/* - Remove include/configs/lubbock.h - Cleanup defined(CONFIG_LUBBOCK) - Move the entry from boards.cfg to doc/README.scrapyard Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | keystone2: net: add keystone ethernet driverKaricheri, Muralidharan2014-04-17-0/+717
|/ | | | | | | | | | | | Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-04-08-1/+1
|\ | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/arm926ejs/mxs/Makefile include/configs/trats.h include/configs/trats2.h include/mmc.h
| * net/designware: align DMA buffer descriptors to D$ lineAlexey Brodkin2014-03-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's important to have ability to flush/invalidate each DMA buffer descriptor individually to prevent incoherency of adjacent BDs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com>
* | drivers: net: cpsw: init phy with gigabit featuresIlya Ledvich2014-03-12-5/+1
|/ | | | | | | | CPSW ia a gigabit device. Use the PHY_GBIT_FEATURES macro to determine phy supported features. Tested on cm_t335. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-10-2/+2
|\
| * drivers: net: cpsw: add support to have phy address from cpsw platform dataMugunthan V N2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
* | net/phy: Correct AR8021 phy_maskHaijun.Zhang2014-03-07-1/+1
| | | | | | | | | | | | | | | | There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
* | net: gem: Add OF initialization supportMichal Simek2014-03-04-0/+42
| | | | | | | | | | | | Gem can be directly initialized from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: emaclite: Fix OF initializationMichal Simek2014-03-04-8/+9
|/ | | | | | | | - Add xilinx_emaclite_of_init to netdev.h - Remove global data pointer from the driver - Add better handling for error state. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-0/+1
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * ar8031/8033/phy:enable autonegotiation for ar8031/8033Zhao Qiang2014-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | SMC91111: Fix compilation warningsBhupesh Sharma2014-02-21-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warning messages coming out of 'drivers/net/smc91111.h' when compiled for 'vexpress_aemv8a': warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Currently this issue seems to surface when SMSC is compiled for 64-bit ARMv8 platforms, so the change is protected under CONFIG_ARM64, so that it doesn't break other existing platforms. In addition this patch tries to fix some checkpatch errors and warnings (others related to camel-casing and volatile usage will be addressed by a later patch). This fix has been tested on both ARMv8 foundation model v1 and v2. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-20-65947/+17
|\ \
| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-20-1/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
| * \ \ Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-2/+6
| |\ \ \
| | * \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-167/+9
| | |\ \ \
generated by cgit v1.1 at 2024-11-06 19:02:27 +0000