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| * net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-04-7/+19
| | | | | | | | | | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+148
| | | | | | | | | | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: mvpp2.c: Add Marvell mvpp2 network driver for Armada 375Stefan Roese2016-04-04-0/+4199
|/ | | | | | | | | | | | This patch adds support for the mvpp2 ethernet controller which is integrated in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4), which has been stripped of the in U-Boot unused portions. Tested on the Marvell Armada 375 eval board db-88f6720. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
* net: phy: Realtek RTL8211B/C PHY ID fixKarsten Merker2016-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Optionally force master mode for RTL PHYMichael Haas2016-03-31-1/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-29-2/+2
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| * driver: net: fsl-mc: Check NULL before pointer dereferencePrabhakar Kushwaha2016-03-29-1/+1
| | | | | | | | | | | | | | | | | | | | NULL pointer should be checked before any dereference. This patch move memest after the NULL pointer check. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * driver: net: fsl-mc: Free dflt_dpio pointer after its usagePrabhakar Kushwaha2016-03-28-1/+1
| | | | | | | | | | | | | | | | Free dflt_dpio pointer after its usage during error handling Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Jose Rivera <german.rivera@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | net: rtl8169: Fix build error when DEBUG is onBin Meng2016-03-27-5/+5
|/ | | | | | | | | When DEBUG_RTL8169 is on, a build error occurs in function 'rtl_init': error: 'dev' undeclared. Fix this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Move CONFIG_RTL8169 to KconfigBin Meng2016-03-22-0/+6
| | | | | | | | | Introduce CONFIG_RTL8169 in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Stephen Warren <swaren@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Move CONFIG_RTL8139 to KconfigBin Meng2016-03-22-0/+6
| | | | | | | | | | Introduce CONFIG_RTL8139 in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> [trini: Fixup MPC8641HPCN* and r2dplus configs] Signed-off-by: Tom Rini <trini@konsulko.com>
* driver: net: fsl-mc: Return from DPAA_exit if boot_status !=0Prabhakar Kushwaha2016-03-21-1/+2
| | | | | | | | | | | | Return value of get_mc_boot_status() in case of failure is not necessary to be -1. So update the error condition check. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reported-by: Yao Yuan <yao.yuan@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
* driver: net: ldpaa_eth: Add support of PHY frameworkPrabhakar Kushwaha2016-03-21-34/+87
| | | | | | | | | | | This patch integrate DPAA2 ethernet driver existing PHY framework. Call phy_connect and phy_config as per available DPMAC id defined in SerDes Protcol. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Kconfig: Move CONFIG_FIT and related options to KconfigSimon Glass2016-03-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are already two FIT options in Kconfig but the CONFIG options are still in the header files. We need to do a proper move to fix this. Move these options to Kconfig and tidy up board configuration: CONFIG_FIT CONFIG_OF_BOARD_SETUP CONFIG_OF_SYSTEM_SETUP CONFIG_FIT_SIGNATURE CONFIG_FIT_BEST_MATCH CONFIG_FIT_VERBOSE CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_RSA Unfortunately the first one is a little complicated. We need to make sure this option is not enabled in SPL by this change. Also this option is enabled automatically in the host builds by defining CONFIG_FIT in the image.h file. To solve this, add a new IMAGE_USE_FIT #define which can be used in files that are built on the host but must also build for U-Boot and SPL. Note: Masahiro's moveconfig.py script is amazing. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Add microblaze change, various configs/ re-applies] Signed-off-by: Tom Rini <trini@konsulko.com>
* net: phy: atheros: Fix problem with phy_reset() clearing BMCRAlison Wang2016-02-26-0/+3
| | | | | | | | | | | | | | | In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-24-1/+131
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| * driver/fm: fdt.c: fix fdt_fixup_fman_firmware() to support ARM platformsQianyu Gong2016-02-24-5/+6
| | | | | | | | | | | | | | | | Use fdt32_to_cpu() to convert the data correctly for both endianness platforms. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fm: fdt: Move fman ucode fixup to driver codeQianyu Gong2016-02-24-0/+129
| | | | | | | | | | | | | | | | | | Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-24-1/+1
| | | | | | | | | | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | net: phy: realtek: Use generic genphy_parse_link() for RTL8211EMichal Simek2016-02-22-1/+9
|/ | | | | | | | | | | | | | | | | | | | The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which ending up in driver failure that link is not up. Log: Zynq> dhcp ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done ethernet@e000b000: No link. There is at least 1ms delay between spddone bit and link up. Use genphy_read_status() instead of realtek implemenation which is working with page 11. Linux driver is also using generic implementation. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-20-5/+5
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| * drivers: at91: clean up peripheral clock codeWenyou Yang2016-02-18-5/+5
| | | | | | | | | | | | | | | | | | | | Due to introducing the new peripheral clock handle functions, use these functions to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> [fixup for missing clk.h in at91_emac.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | net: phy: marvell: Fix problem with phy_reset() clearing BMCRStefan Roese2016-02-18-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: marvell: Call phy_reset() where possibleStefan Roese2016-02-18-21/+2
|/ | | | | | | | | | | | | Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers: net: keystone_net: convert driver to adopt device driver modelMugunthan V N2016-02-08-40/+433
| | | | | | | Adopt keystone_net driver to adopt device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* drivers: net: phy: micrel: fix build errors with CONFIG_DM_ETHMugunthan V N2016-02-08-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or CONFIG_PHY_MICREL_KSZ9021 there is a build error. Fixing this by adding proper ifdefs drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = ^ drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type static const struct ksz90x1_reg_field ksz9031_clk_grp[] = ^ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type struct ksz90x1_ofcfg ofcfg[] = { ^ drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function) { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, ^ drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function) { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, ^ drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration] ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); ^ drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable] struct ksz90x1_ofcfg ofcfg[] = { ^ drivers/net/phy/micrel.c: At top level: drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable] static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = ^ drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable] static const struct ksz90x1_reg_field ksz9031_clk_grp[] = ^ scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed make[1]: *** [drivers/net/phy/micrel.o] Error 1 Makefile:1201: recipe for target 'drivers/net/phy' failed make: *** [drivers/net/phy] Error 2 make: *** Waiting for unfinished jobs.... Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2016-02-08-7/+9
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| * net: davinci_emac: fix NULL check after pointer dereferenceVishwas Srivastava2016-02-06-1/+3
| | | | | | | | | | | | | | | | | | | | | | NULL check is made after the pointer dereference. This patch fixes this issue. Signed-off-by: Vishwas Srivastava <vishu.kernel@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * net: fix wrong initialization in davinci-emac driverVishwas Srivastava2016-02-06-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | emac module of the davinci platform supports only 8 tx and 8 rx channels (total 16). emac driver for davinci platform, however, while doing initialization of the dma descriptor head pointers, wrongly initializes the 16 head pointers (instead of 8) for tx dma and 16 head pointers (insted of 8) for rx dma, which is wrong. The result is, that this register initilization spills over the other registers which was not intended and is undesirable. This patch fixes this problem. Signed-off-by: Vishwas Srivastava <vishu.kernel@gmail.com> CC: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * Use correct spelling of "U-Boot"Bin Meng2016-02-06-4/+4
| | | | | | | | | | | | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* | net: e1000: Convert to use DM PCI APIBin Meng2016-02-05-1/+78
| | | | | | | | | | | | | | Update this driver to use proper DM PCI APIs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | net: designware: Use dm_pci_mem_to_phys() in the probe routineBin Meng2016-02-05-3/+1
| | | | | | | | | | | | | | Convert to use native DM PCI API dm_pci_mem_to_phys(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | net: pch_gbe: Convert to use DM PCI APIBin Meng2016-02-05-16/+13
|/ | | | | | | Use native DM PCI APIs instead of legacy compatible ones. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-2/+19
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| * net: macb: Not all the GEM are gigabit capableGregory CLEMENT2016-01-27-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the initialization of PHY the gigabit bit capable is set if the controller is a GEM. However, for sama5d2 and sama5d4, the GEM is configured to support only 10/100. Improperly setting the GBE capability leads to an unresponsive MAC controller. This patch fixes this behavior allowing using the gmac with these SoCs. Suggested-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-02-1/+2
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| * | driver: net: fsl-mc: Update print to reflect correct stringPrabhakar Kushwaha2016-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update printf with dpbp_exit to match with previous function call. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Memset dprc_cfg before configuringPrabhakar Kushwaha2016-02-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | drivers: net: Add ethernet driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+899
| | | | | | | | | | | | | | | | | | | | | | | | This driver implements MAC and MII layer of the ethernet controller. Network data transfer is handled by controller internal DMA engine. Ethernet controller is configurable through device-tree file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal2016-02-01-0/+10
|/ / | | | | | | | | | | | | | | | | Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-213/+832
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| * | net: phy: implements probe for Cortina phyShaohui Xie2016-01-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cortina phy cannot support soft reset, this commit implements probe for Cortina PHY to tell phylib to skip phy soft reset by setting PHY_FLAG_BROKEN_RESET in flags. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: introduce a quirk PHY_FLAG_BROKEN_RESETShaohui Xie2016-01-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver always performs a phy soft reset when connecting the phy device, but soft reset is not always supported by a phy device, so introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip soft reset. This commit uses 'flags' of phy device structure to store the quirk. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: fix divisor value for KSZ9031 phy skewDinh Nguyen2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60. For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay. With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet. References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Use 'autoneg' flag from phydevAlexandre Messier2016-01-28-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the 'autoneg' flag available in phydev when checking if autoneg is in use. The previous implementation was checking directly in the PHY if autoneg was supported. Some PHYs will report that autoneg is supported, even when it is disabled. Thus it is not possible to use that bit to determine if autoneg is currently in use or not. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Set ANRESTART in setup_forcedAlexandre Messier2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When configuring a PHY in fixed (forced) link mode, in order for the changes to be applied, either one of these conditions must be triggered: 1- PHY is reset 2- Autoneg is restarted 3- PHY transitions from power-down to power-up Neither of these is currently done, so effectively the fixed link configuration is not applied in the PHY. Fix this by setting the Autoneg restart bit. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: Disable B_CAST on configAlexandre Messier2016-01-28-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0 is considered as a broadcast address; the PHY will respond even if it is not its configured (pinstrapped) address. This feature is enabled by default. The Linux kernel disables that feature at initialisation, but not before it probes the MDIO bus. This causes an issue, because a PHY at address 3 will be discovered at addresses 0 and 3, but will then only respond at address 3. Because Linux attaches the first PHY it discovers on 'eth0', it will attach the PHY from address 0, which will never answer again. Fix the issue by disabling the broadcast feature in U-Boot, before Linux is started. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/designware: add support of max-speed device tree propertyAlexey Brodkin2016-01-28-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This property allows to specify fastest connection mode supported by the MAC (as opposed to features of the phy). There are situations when phy may handle faster modes than the MAC (or even it's particular implementation or even due to CPU being too slow). This property is a standard one in Linux kernel these days and some boards do already use it in their device tree descriptions. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sonic Zhang <sonic.zhang@analog.com> cc: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/designware: do explicit port selection for 1Gb modeAlexey Brodkin2016-01-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation only sets "port select" bit for non-1Gb mode. That works fine if GMAC has just exited reset state but we may as well change connection mode in runtime. Then we'll need to reprogram GMAC for that new mode of operation and if previous mode was 10 or 100 Mb and new one is 1 Gb we'll need to reset port mode bit. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sonic Zhang <sonic.zhang@analog.com> cc: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers/net/phy: introduce phy_set_supported()Alexey Brodkin2016-01-28-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new function will allow MAC drivers to override supported capabilities of the phy. It is required when MAC cannot handle all speeds supported by phy. For example phy supports up-to 1Gb connections while MAC may only work in modes up to 100 or even 10 Mbit/sec. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit v1.1 at 2024-11-14 03:39:26 +0000