summaryrefslogtreecommitdiff
path: root/drivers/net
Commit message (Collapse)AuthorAgeLines
...
| * | driver: net: fsl-mc: Update print to reflect correct stringPrabhakar Kushwaha2016-02-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update printf with dpbp_exit to match with previous function call. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver: net: fsl-mc: Memset dprc_cfg before configuringPrabhakar Kushwaha2016-02-01-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All fields of struct dprc_cfg are not being configured while creating child container. "Not" configured fields are assumed to be 0. So memset dprc_cfg before configuring the fields. Signed-off-by: Itai Katz <itai.katz@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | drivers: net: Add ethernet driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+899
| | | | | | | | | | | | | | | | | | | | | | | | This driver implements MAC and MII layer of the ethernet controller. Network data transfer is handled by controller internal DMA engine. Ethernet controller is configurable through device-tree file. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* | | drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal2016-02-01-0/+10
|/ / | | | | | | | | | | | | | | | | Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-213/+832
|\ \
| * | net: phy: implements probe for Cortina phyShaohui Xie2016-01-28-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cortina phy cannot support soft reset, this commit implements probe for Cortina PHY to tell phylib to skip phy soft reset by setting PHY_FLAG_BROKEN_RESET in flags. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: introduce a quirk PHY_FLAG_BROKEN_RESETShaohui Xie2016-01-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current driver always performs a phy soft reset when connecting the phy device, but soft reset is not always supported by a phy device, so introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip soft reset. This commit uses 'flags' of phy device structure to store the quirk. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: fix divisor value for KSZ9031 phy skewDinh Nguyen2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60. For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay. With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet. References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Use 'autoneg' flag from phydevAlexandre Messier2016-01-28-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the 'autoneg' flag available in phydev when checking if autoneg is in use. The previous implementation was checking directly in the PHY if autoneg was supported. Some PHYs will report that autoneg is supported, even when it is disabled. Thus it is not possible to use that bit to determine if autoneg is currently in use or not. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: Set ANRESTART in setup_forcedAlexandre Messier2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When configuring a PHY in fixed (forced) link mode, in order for the changes to be applied, either one of these conditions must be triggered: 1- PHY is reset 2- Autoneg is restarted 3- PHY transitions from power-down to power-up Neither of these is currently done, so effectively the fixed link configuration is not applied in the PHY. Fix this by setting the Autoneg restart bit. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: micrel: Disable B_CAST on configAlexandre Messier2016-01-28-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0 is considered as a broadcast address; the PHY will respond even if it is not its configured (pinstrapped) address. This feature is enabled by default. The Linux kernel disables that feature at initialisation, but not before it probes the MDIO bus. This causes an issue, because a PHY at address 3 will be discovered at addresses 0 and 3, but will then only respond at address 3. Because Linux attaches the first PHY it discovers on 'eth0', it will attach the PHY from address 0, which will never answer again. Fix the issue by disabling the broadcast feature in U-Boot, before Linux is started. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/designware: add support of max-speed device tree propertyAlexey Brodkin2016-01-28-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This property allows to specify fastest connection mode supported by the MAC (as opposed to features of the phy). There are situations when phy may handle faster modes than the MAC (or even it's particular implementation or even due to CPU being too slow). This property is a standard one in Linux kernel these days and some boards do already use it in their device tree descriptions. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sonic Zhang <sonic.zhang@analog.com> cc: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net/designware: do explicit port selection for 1Gb modeAlexey Brodkin2016-01-28-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation only sets "port select" bit for non-1Gb mode. That works fine if GMAC has just exited reset state but we may as well change connection mode in runtime. Then we'll need to reprogram GMAC for that new mode of operation and if previous mode was 10 or 100 Mb and new one is 1 Gb we'll need to reset port mode bit. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sonic Zhang <sonic.zhang@analog.com> cc: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers/net/phy: introduce phy_set_supported()Alexey Brodkin2016-01-28-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new function will allow MAC drivers to override supported capabilities of the phy. It is required when MAC cannot handle all speeds supported by phy. For example phy supports up-to 1Gb connections while MAC may only work in modes up to 100 or even 10 Mbit/sec. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: genphy: Allow overwriting featuresSascha Hauer2016-01-28-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_set_phy_supported allows overwiting hardware capabilities of a phy with values from the devicetree. This does not work with the genphy driver though because the genphys config_init function will overwrite all values adjusted by of_set_phy_supported. Fix this by initialising the genphy features in the phy_driver struct and in config_init just limit the features to the ones the hardware can actually support. The resulting features are a subset of the devicetree specified features and the hardware features. This is a copy of the patch from Linux kernel, see http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: ensure Gigabit features are masked off if requestedFlorian Fainelli2016-01-28-18/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet MAC, the driver will restrict the phydev->supported modes to mask off Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features set by default in MII_CTRL1000, it will keep advertising these feature, so by the time we call genphy_config_advert(), the condition on phydev->supported having the Gigabit features on is false, and we do not update MII_CTRL1000 with updated values, and we keep advertising Gigabit features, eventually configuring the PHY for Gigabit whilst the Ethernet MAC does not support that. This patches fixes the problem by ensuring that the Gigabit feature bits are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit PHY, and then, if Gigabit features are supported, setting those and updating MII_CTRL1000 accordingly. This is a copy of patch from Linux kernel, see http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Use priv->tbiaddr to initialize TBI PHY addressBin Meng2016-01-28-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver, it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we can get this from device tree. Update the bindings doc as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Add driver model ethernet supportBin Meng2016-01-28-0/+186
| | | | | | | | | | | | | | | | | | | | | | | | This adds driver model support to Freescale TSEC ethernet driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Use tsec_private pointer as the parameter for internal routinesBin Meng2016-01-28-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | For internal routines like redundant_init(), startup_tsec() and init_phy(), change to use tsec_private pointer as the parameter. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Adjust orders to avoid forward declaration of tsec_send()Bin Meng2016-01-28-105/+103
| | | | | | | | | | | | | | | | | | | | | | | | Adjust static functions in a proper order so that forward declaration of tsec_send() can be avoided. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Move rxbd and txbd to struct tsec_privateBin Meng2016-01-28-37/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | rxbd and txbd are declared static with 8 byte alignment requirement, but they can be put into struct tsec_private as well and are natually aligned to 8 byte. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: Move rx_idx and tx_idx to struct tsec_privateBin Meng2016-01-28-28/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present rx_idx and tx_idx are declared as static variables in the driver codes. To support multiple interfaces, move it to struct tsec_private. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: tsec: fsl_mdio: Fix several cosmetic issuesBin Meng2016-01-28-29/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the tsec and fsl_mdio driver codes a little bit, by: - Fix misuse of tab and space here and there - Use correct multi-line comment format - Replace license identifier to GPL-2.0+ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: vsc9953: Add LAG supportCodrin Ciubotariu2016-01-28-1/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | You can now configure LAG on VSC9953's ports using the command: ethsw [port <port_no>] aggr {[help] | show | <lag_group_no>} A port must belong to a single LAG. By default, a port belongs to a LAG equal to the port's number. For each frame, a hash will be calculated based on Source/Destination MAC addresses, Source/Destination IP(v4/v6) addresses, Source/Destination ports. This hash will be used to select a single egress port from LAG. This also assures that frames from the same flow will always have the same egress port. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | drivers: net: vsc9953: Fix FDB aging timeCodrin Ciubotariu2016-01-28-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | By default, the aging period is set to 0, so the dynamic FDB entries are never removed. This patch sets the aging time to 300 seconds. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: phy: do not read configuration register on resetStefan Agner2016-01-28-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing a software reset, the reset flag should be written without other bits set. Writing the current state will lead to restoring the state of the PHY (e.g. Powerdown), which is not what is expected from a software reset. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Michael Welling <mwelling@ieee.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-27-8/+268
|\ \ \
| * | | driver: net: fsl-mc: Remove portal id hard-codingPrabhakar Kushwaha2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management Complex firmware 9.0 has fixed the issue of dprc_destroy_container i.e. the used portal is not return to the free pool. Which was resulting in error ethernet driver want to use this portal via either DPL or dynamically in Linux. Hard-coding of portal id is removed. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: ldpaa: Add debug info of printing DPMAC statsPrabhakar Kushwaha2016-01-27-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add debug information prints to provide DPMAC statistics - Number of bytes received - Number of received and discard frames - Number of bytes transferred - Number of frames transferred etc. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: ldpaa: Increase num of buffers for a poolPrabhakar Kushwaha2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management Complex FW 9.0 set the hardware depletion to be 20 buffers in order to support multiple pools in DPNI. This requires driver to fill the pool with at least 21 to be able to receive frames. So, Increase number of buffers for a pool. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: ldpaa: Report back only error frames for txPrabhakar Kushwaha2016-01-27-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management Complex FW 9.0 puts a new requirement to provide Tx confirmation and error queue configuration by calling dpni_set_tx_conf API. Configure report of only error frames for a tx frame. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: fsl-mc: Prepare extended cfg for DPNI createPrabhakar Kushwaha2016-01-27-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Management Complex FW 9.0 puts a new requirement to prepare extended parameters which should be provided as input in dpni_create. extended parameters includes traffic class and IP reassembly configurations. So prepare extended parameters with default "0" as input for dpni_create. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: fsl-mc: flib changes for MC FW 9.0.0Prabhakar Kushwaha2016-01-27-3/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MC firmware version 9.0.0 contains - Support of new APIs - Update in existing APIs - Change in Major and minor version of DPAA2 objects This patch contains modifications in FLIB files to support new MC firmware version. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | driver: net: fsl-mc: Add version check for MC objectsPrabhakar Kushwaha2016-01-27-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check and compare version of management complex's object with the version supported by Freescale ldpaa2 ethernet driver. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | drivers: net: fsl_mc: Compare pointer value qbman_swp_mc_startPratiyush Mohan Srivastava2016-01-25-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code compares the return pointer of function qbman_cena_write_start with NULL. Instead the value of the return pointer should be compared. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | net: xilinx_ll_temac: Fix string overflowRicardo Ribalda Delgado2016-01-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Size of this snprintf "lltemac.%lx" is bigger than 16 characters. Replacing it with "ll_tem.%lx" Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: zynq: Change MDC setup for arm64Michal Simek2016-01-27-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: phy: ti: Enable automatic crossover modeMichal Simek2016-01-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable automatic crossover cable detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Move emaclite to KconfigMichal Simek2016-01-27-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PHYLIB and MII dependencies and enable it by default for Microblaze. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Let core to handle received packetMichal Simek2016-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Pass pointer to core to handle packet. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: emaclite: Rename start and stop functionsMichal Simek2016-01-27-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Rename start and stop functions to align with DM functions names. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: emaclite: Move driver to DMMichal Simek2016-01-27-68/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move driver to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Use indirect access in emaclite_recvMichal Simek2016-01-27-52/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When IP is configured with pong buffers, IP is receiving packets to ping and then to pong buffer and than ping again. The original logic in the driver remains there that when ping buffer is free, pong buffer is checked too and return if both are free. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: emaclite: Use indirect reg access in sendMichal Simek2016-01-27-30/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original logic in the driver was exchanging buffers which are used for sending packet and tx_ping and tx_pong buffers were exchanged all the time to ensure that IP has enough time to send the packet out. Based on this "feature" send function was using nextbuffertouse variable to save which buffer should be used. Before this algorithm was called driver checked that there is free buffer available. This checking remains in the driver but driver tries to use tx_ping first if available. If not, tx_pong buffer is used instead. To reach this code the original condition is met that at least one of the buffer should be available. Testing doesn't show any performance drop when this patch is applied. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Remove XEL_TSR_XMIT_ACTIVE_MASK flagMichal Simek2016-01-27-13/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This flag is not documented anywhere in the latest documentation that's why this patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Fix logic around available TX buffersMichal Simek2016-01-27-16/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify logic how to find out if there is free TX buffer. Both buffers are checked all the time that's why logic around order can be removed. Also add check when only one buffer is available. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Use indirect register access for TX resetMichal Simek2016-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move to use indirect register access when timeout expires for resetting TX buffers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Use indirect register access for rx_ping/pongMichal Simek2016-01-27-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Do initialization via indirect register access. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | net: emaclite: Use indirect register access for tx_ping/pongMichal Simek2016-01-27-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Do initialization via indirect register access. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | | net: emaclite: Convert MDIO to use register offsetMichal Simek2016-01-27-36/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use u-boot coding style how to setup and access MDIO bus. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit v1.1 at 2024-10-30 19:32:20 +0000