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* Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h headerSimon Glass2015-09-11-0/+3
| | | | | | | Now that we have a new header file for cache-aligned allocation, we should move the stack-based allocation macro there also. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: Remove xaeniax boardSimon Glass2015-09-11-72/+1
| | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: designware: Fix build warningsBin Meng2015-09-09-4/+4
| | | | | | | | | | | | | | | | | | | When building dm version of designware eth driver on a platform with 64-bit phys_addr_t, it reports the following warnings: drivers/net/designware.c: In function 'designware_eth_probe': drivers/net/designware.c:599:2: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'phys_addr_t' [-Wformat] drivers/net/designware.c:600:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] drivers/net/designware.c:601:21: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: pch_gbe: Add Kconfig optionBin Meng2015-09-09-0/+13
| | | | | | Add Kconfig option in preparation for moving board to use Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* net: pch_gbe: Convert to driver modelBin Meng2015-09-09-62/+73
| | | | | | | | | | | This commit converts pch_gbe ethernet driver to driver model. Since this driver is only used by Intel Crown Bay board, the conversion does not keep the non-dm version. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: altera_tse: Zap unused variableMarek Vasut2015-09-04-2/+0
| | | | | | | | | Zap variable which is set but never used. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-09-02-7/+20
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| * net/fman: Support both new and legacy FMan CompatiblesIgal Liberman2015-09-01-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman@freescale.com> Tested-by: Xing Lei <xing.lei@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-02-5/+9
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| * | net: fec: do not access reserved register for i.MX6ULPeng Fan2015-09-02-5/+9
| |/ | | | | | | | | | | | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de>
* | ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-01-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net: phy/vitesse: Add support for VSC8584 phyPrabhakar Kushwaha2015-09-01-0/+11
|/ | | | | | | | | | Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: e1000: Fix build warnings for 32-bitBin Meng2015-08-26-4/+5
| | | | | | | | | | | | | | | | commit 6497e37 "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: e1000: Add Kconfig optionsSimon Glass2015-08-21-7/+32
| | | | | | | Add Kconfig options in preparation for moving boards to use Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: e1000: Convert to driver modelSimon Glass2015-08-21-0/+142
| | | | | | | | | Update this driver to support driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* net: e1000: Prepare for driver model conversionSimon Glass2015-08-21-200/+245
| | | | | | | | | | | | | | | Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid using it in the driver unless necessary. Most of the time it is better to pass the private driver pointer anyway. Also refactor the code so that code that the driver model implementation will share are available in functions that can be called. Add stubs where necessary. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* net: e1000: Move #include of common.h to the C filesSimon Glass2015-08-21-1/+2
| | | | | | | | | | | We cannot currently include any header files in the C files since common.h needs to be included first, and it is in the header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-on: Apalis T30 2GB on Apalis Evaluation Board
* net: e1000: Support 64-bit physical addressMingkai Hu2015-08-21-4/+4
| | | | | | | | | High 32-bit address is needed when u-boot runs in 64-bit space. Tested on armv8-based LS2085ARDB. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-17-1/+0
| | | | | | | | | | | | | This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* net: lpc32xx: eth buffers base configSylvain Lemieux2015-08-13-3/+5
| | | | | | | | Add support to specify the Ethernet buffer base address; if none are supply by the board, the default value is use (from existing code). Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: e1000: Increase autoneg timeout to 8 secondsStefan Roese2015-08-12-2/+2
| | | | | | | | | | | The current 4.5 timeout for the autonegotiation are not enough to complete it on my platform. Using the Intel E1000 PCIe card in the Marvell db-mv784mp-gp eval board. So lets increase the timeout to 8 seconds. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org>
* net: phy: broadcom: Add BCM Cygnus PHYJiandong Zheng2015-08-11-0/+29
| | | | | | | | Add Ethernet PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: delay only if reset handler is registeredJörg Krause2015-08-11-3/+5
| | | | | | | | With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only reset if a reset handler is registered. If there is no reset handler there is no need to wait for a device to come out of the reset. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* net: phy: fix data type of phy_idJörg Krause2015-08-11-1/+1
| | | | | | phy_id is declared as u32 in create_phy_by_mask and in struct phy_device. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* qoriq eth.c bugfix: handle received corrupted frames correctlyDaniel Inderbitzin2015-08-11-2/+3
| | | | | | | | The rxbd is not correctly handled in case of a frame physical error (FPE) or frame size error (FSE). The rxbd must be cleared and advanced in case of an error to avoid receive stall. Signed-off-by: Daniel Inderbitzin <daniel.inderbitzin@gmail.com>
* net: lpc32xx: add RMII phy mode supportVladimir Zapolskiy2015-08-11-3/+17
| | | | | | | | | | | | | | | | | | LPC32xx MAC and clock control configuration requires some minor quirks to deal with a phy connected by RMII. It's worth to mention that the kernel and legacy BSP from NXP sets SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011 and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also in my tests an SMSC LAN8700 phy device connected over RMII seems to work correctly without touching this bit. Add support of RMII, if CONFIG_RMII is defined, this option is aligned with a number of boards, which already define the same config value. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* net: lpc32xx: improve MAC configuration on reset and initializationVladimir Zapolskiy2015-08-11-18/+15
| | | | | | | | | | | | | | | | | | This change rearranges general MAC configuration and PHY specific configuration of MAC registers (duplex mode and speed), before this change set bits related to PHY configuration in MAC2 and COMMAND registers are rewritten by the following writing to the registers. Without the change auto negotiation on boot quite often is not completed in reasonable time: Waiting for PHY auto negotiation to complete......... TIMEOUT ! Additionally MAC1_SOFT_RESET clear bit is removed since it is done in preceding lpc32xx_eth_initialize() and in lpc32xx_eth_halt(), instead added missing MCFG_RESET_MII_MGMT on device initialization. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* net: lpc32xx: connect MAC to phy with CONFIG_PHY_ADDR idVladimir Zapolskiy2015-08-11-1/+1
| | | | | | | | | | | The lpc32xx_eth_phylib_init() function is capable to connect LPC32XX MAC to some specified phy by phy id, by chance the single user of lpc32xx_eth has CONFIG_PHY_ADDR set to 0, however other boards may have non-zero CONFIG_PHY_ADDR value, fix it. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: lpc32xx: correct command register reset valueVladimir Zapolskiy2015-08-11-1/+1
| | | | | | | | | | | | | | | | | | According to LPC32x0 User Manual the following bits in Command register 0x3106_0100 are defined: Bit Symbol 2 - Unused 3 RegReset 4 TxReset 5 RxReset Fix wrong (1-bit shifted right) COMMAND_RESETS value, which sets an unused bit, but neglects RxReset. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: davinci_emac: don't teardown inactive rx channelJeroen Hofstee2015-08-11-1/+2
| | | | | | | | | | Tearing down an unitialized rx channel causes a pending address hole event to be queued. When booting linux it will report this pending as something like "Address Hole seen by USB_OTG at address 57fff584", since u-boot did not handled this interrupt. Prevent that by not tearing down the rx channel, when not receiving. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* net: Add support for Marvell 88E1510 PHYClemens Gruber2015-08-11-0/+30
| | | | | | | | | | | Support the 88E1510 PHY which is very similar to the 88E1518. I also set the INTn output and configured the LEDs. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Improve 88E151x PHY initializationClemens Gruber2015-08-11-14/+23
| | | | | | | | | | | - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: macb: add gmac multi-queue supportWu, Josh2015-08-11-0/+42
| | | | | | | | | | | | | | | This patch refer to linux kernel commit: d8b763e1e79f net/macb: add TX multiqueue support for gem by: Cyrille Pitchen 1. macb driver will check the register to find how many queues support for this chip. 2. Then as we only use queue0 for tx, so we will set up all other queues use a dummy descriptor, which USED bit is set. So those queues are not used. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy: set led for rtl8211f phyShengzhou Liu2015-08-11-0/+8
| | | | | | | Initialize LCR rigister to configure green LED for Link, yellow LED for Active. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* e1000: remove unnecessary clearing of SWSM.SWSM_SMBITim Harvey2015-08-11-4/+0
| | | | | | | | | | | | | | | | | | | | | remove unnecessary clearing of SWSM.SWSM_SMBI when obtaining the SW semaphore. This was introduced in 951860634fdb557bbb58e0f99215391bc0c29779 while adding i210 support and should be now resolved by releasing the semaphore when no longer needed. Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Marek Vasut <marex@denx.de> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* Revert "e1000: fix sw fw sync on igb i210/i211"Tim Harvey2015-08-11-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 17da7120249bfdef877f46be5bbcb3cc01212eb9. The i210/i211 do have the SW_FW_SYNC (0x5b5c) register and this is what should be used when acquiring the semaphore. I believe the issue that this patch was trying to resolve is now resolved by properly releasing the semaphore once no longer needed. Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Marek Vasut <marex@denx.de> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* e1000: releasing semaphore once no longer neededTim Harvey2015-08-11-0/+22
| | | | | | | | | | | | | | | | | | | | Once the hwsw semaphore is acquired, it must be released when access to the hw is completed. Without this subsequent calls to acquire will timeout obtaining the semaphore. Cc: Marcel Ziswiler <marcel@ziswiler.com> Cc: Marek Vasut <marex@denx.de> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Naveen Burmi <NaveenBurmi@freescale.com> Cc: Po Liu <po.liu@freescale.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Alison Wang <alison.wang@freescale.com> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
* net: designware: Rename the driver var name to eth_designwareMarek Vasut2015-08-08-1/+1
| | | | | | | | | The driver variable name is eth_sandbox, which is probably a copy-paste mistake. Fix it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: designware: Add SoCFPGA GMAC DT compatible stringMarek Vasut2015-08-08-0/+1
| | | | | | | | Add the OF compatible property to match the SoCFPGA GMAC. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers/fsl-mc: flib changes for mc 8.0.0Prabhakar Kushwaha2015-08-03-129/+261
| | | | | | | | | MC firware version 8.0.0 contains new command flags. This patch contains modifications in FLIB files to support the new command flags. Signed-off-by: Itai Katz <itai.katz@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-15/+5
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| * net: fec_mxc: remove useless struct nbufAlbert ARIBAUD \(3ADEV\)2015-07-10-15/+5
| | | | | | | | | | | | | | | | This locally defined struct is actually only used once and as an opaque type. Remove it for clarity. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-07-28-7/+19
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| * | net: gem: Extend timeout valueMichal Simek2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | Extend time for MDIO. (Because of zed board) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: gem: Setting up WRAP bit for one TX bdMichal Simek2015-07-28-1/+2
| | | | | | | | | | | | | | | | | | | | | Setting up WRAP bit to indicate that this is the last TX BD in the chain. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: gem: Increase the Rx buffer descriptors to 32Siva Durga Prasad Paladugu2015-07-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Increase the Rx Buffer descriptors to 32. This will avoid Rx buffer descriptors overflow if more packets were received at one shot before we process the received ones. This fixes the issue of intermittent timeouts during tftp on a 1Gb connection with tftp server running on windows. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: gem: Flush the rx buffers while transmittingSiva Durga Prasad Paladugu2015-07-28-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Flush and invalidate the rx buffers while sending the tx packet it self as armv8 does flush also while doing invalidation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynqmp: gem: Set data bus width to 64bit for arm64Siva Durga Prasad Paladugu2015-07-28-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | Set the data bus width to 64-bit AMBA Databus width in config register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | keystone2: net: add mcast function to keyston2 Ethernet driverVitaly Andrianov2015-07-27-0/+10
|/ / | | | | | | | | | | | | | | | | | | | | The MCAST_TFTP support requires that network drivers has mcast functon implemented. This commit adds dummy keystone2_eth_bcast_addr() to meet the requirement. As far as the driver doesn't use ALE and doesn't filter any incoming packets, the function is empty. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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