summaryrefslogtreecommitdiff
path: root/drivers/net
Commit message (Collapse)AuthorAgeLines
* NET: phy: add 88E1310 PHY initializationSebastian Hesselbarth2013-06-24-0/+48
| | | | | | This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* net: add ICPlus PHY driverYegor Yefremov2013-06-24-0/+98
| | | | | | | The driver code was taken from Linux kernel source: drivers/net/phy/icplus.c Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* phy: export genphy_parse_link()Yegor Yefremov2013-06-24-1/+1
| | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* net: Add sunxi (Allwinner) wemac driverHenrik Nordström2013-06-24-0/+534
| | | | | | | | | | This patch adds support for the WEMAC, the ethernet controller included in the Allwinner A10 SoC. It will get used in the upcoming A10 board support. From: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-3/+1
|\ | | | | | | | | Conflicts: drivers/serial/Makefile
| * net: fec_mxc: Add support for Vybrid VF610Alison Wang2013-06-03-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FEC support for Vybrid VF610 platform. In function fec_open(), RCR register is only set as RGMII mode. But RCR register should be set as RMII mode for VF610 platform. This configuration is already done in fec_reg_setup(), so this piece of code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-12/+133
|\ \ | |/ |/| | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/phy: fix select line for TN80xxShaohui Xie2013-05-24-2/+14
| | | | | | | | | | | | | | | | | | | | TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-4/+113
| |\
| | * net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * net/fm: fixup ethernet for mEMACShengzhou Liu2013-05-14-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-14-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | smc911x: fix the timeout detectionMasahiro Yamada2013-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | | If timeout is occurred at the while loop above, the value of 'timeout' is -1, not 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | blackfin: The buf variable in bfin_mac.c is not used and produces warning,Marek Vasut2013-05-13-2/+0
| |/ | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-0/+120
|\ \
| * | phy: add support for ET1011C physMatt Porter2013-05-10-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | cpsw: add support for TI814x slave_regs differencesMatt Porter2013-05-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-0/+17
|\ \ \ | |/ / |/| / | |/
| * fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+17
| | | | | | | | | | | | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | net: gem: Add support for phy autodetectionMichal Simek2013-04-30-0/+51
| | | | | | | | | | | | | | Autodetect phy if phyaddress is setup to -1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Preserve clk on emio interfaceDavid Andrey2013-04-30-3/+9
| | | | | | | | | | | | | | | | | | | | | | Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL if the Ethernet interface is connect on EMIO Do not enable emio for this standard board configuration for now. Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Pass phy address to initDavid Andrey2013-04-30-6/+2
| | | | | | | | | | | | | | | | | | Pass the PHY address to the driver init to allow parallel use of both interfaces Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-15/+38
| | | | | | | | | | | | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Do not initialize BDs againMichal Simek2013-04-30-39/+47
| | | | | | | | | | | | | | | | | | | | | | BDs can be correctly setup just once and init function performs only phy autodetection and enabling RX/TX. RX/TX are disabled in halt function. This patch solves the problem with repeatable tftp transfers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Simplify return path in zynq_gem_recvMichal Simek2013-04-30-3/+1
| | | | | | | | | | | | | | Remove one return from the code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Remove WRAP bit from TX buffer descriptionMichal Simek2013-04-30-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Removing this bit causes that frame is sent only once. (With wrap big one packet has been sent several times which dramatically decrease throughput) TRM: (Table 16-3: Tx Buffer Descriptor Entry) Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: phy: Define Marvell 88e1518 phyMichal Simek2013-04-30-0/+11
|/ | | | | | | | This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* Consolidate bool typeYork Sun2013-04-01-490/+458
| | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* am33xx: Add required includes to some omap/am33xx codeTom Rini2013-03-24-0/+1
| | | | | | | | | | | | | - In arch/arm/cpu/armv7/omap-common/timer.c, drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files that the driver needs but had been relying on <config.h> to bring in. - In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h> - In am335x_evm.h and pcm051.h don't globally include <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h> as that is the only include which defines things the config uses. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
* Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-3/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * net: Use new numeric setenv functionsSimon Glass2013-02-28-3/+1
| | | | | | | | | | | | Use setenv_ulong(), setenv_hex() and setenv_addr() in net/ Signed-off-by: Simon Glass <sjg@chromium.org>
* | am335x: cpsw: optimize cpsw_send to increase network performanceMugunthan V N2013-03-11-2/+18
|/ | | | | | | | | | Before submitting packets to cpdma, phy status is updated on every packet which leads to delay in packet send intern reduces the Ethernet performance. Checking mdio status for each packet will reduce timetaken to send a packet and there by increasing the Ethernet performance. With this the performance is increased from 208KiB/s to 375KiB/s on EVMsk Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-125/+169
|\
| * net: fec_mxc: get phydev before fec_probeTroy Kisky2013-01-28-43/+76
| | | | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * net: fec_mxc: only call phy_connect in fec_probeTroy Kisky2013-01-28-21/+12
| | | | | | | | | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * net: fec_mxc: use fec_set_dev_name to set nameTroy Kisky2013-01-28-8/+8
| | | | | | | | | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * phy: add phy_find_by_mask/phy_connect_devTroy Kisky2013-01-28-50/+78
| | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to try a range of possible phy addresses to connect. Also, an ethernet device is not required to use phy_find_by_mask leading to better separation of mii vs ethernet, as suggested by Andy Fleming. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * net: fec_mxc: have fecmxc_initialize call fecmxc_initialize_multiTroy Kisky2013-01-28-16/+8
| | | | | | | | | | | | | | Having only one call to fec_probe will ease the changing of its parameters. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * net: fec_mxc: change fec_mii_setspeed parameterTroy Kisky2013-01-28-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Only the hardware ethernet registers are needed for this function, so don't pass the more general structure. I'm trying to separate MII and fec. This also fixes MX28 fec_mii_setspeed use on secondary ethernet port This was found by inspection of the code and should be checked on real hardware. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
| * net: fec_mxc: delete CONFIG_FEC_MXC_MULTITroy Kisky2013-01-28-1/+1
| | | | | | | | | | | | | | It is more logical to test for CONFIG_FEC_MXC_PHYADDR to determine whether to define the function fecmxc_initialize. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* | ppc: Move mpc512x clocks to arch_global_dataSimon Glass2013-02-04-1/+1
| | | | | | | | | | | | Move ips_clk and csb_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ppc: Move mpc5xxx clocks to arch_global_dataSimon Glass2013-02-04-3/+6
| | | | | | | | | | | | Move ipb_clk and pci_clk into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* | powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-0/+79
|/ | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mv88e61xx: refactor PHY and SWITCH level-codeAlbert ARIBAUD2013-01-09-192/+342
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-1/+4
|\ | | | | | | | | This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
| * am335x: cpsw: make phy address configurableYegor Yefremov2012-12-10-1/+4
| | | | | | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | net: sh_eth: add support for SH7752Yoshihiro Shimoda2012-12-15-4/+4
| | | | | | | | | | | | | | | | SH7752 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit v1.1 at 2024-12-20 00:43:51 +0000