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* e1000: add i211 and unprogrammed i210/i211 supportMarcel Ziswiler2014-10-28-0/+6
| | | | | | | This patch adds support for i211 as well as unprogrammed aka tools only i210/i211 chip support. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* e1000: fix sw fw sync on igb i210/i211Marcel Ziswiler2014-10-27-2/+5
| | | | | | | | | I finally had a look at the datasheet and spotted an additional register address difference between regular E1000 and i210/i211 chips. This patch fixes this and now successfully works on programmed i210/i211 as well as unprogrammed i211. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* net/e1000: Fix EEPROM access errorYork Sun2014-10-27-1/+1
| | | | | | | | | | | | Commit 951860634fdb557bbb58e0f99215391bc0c29779 may have changed the logic unintentially from "if (!(swfw_sync & (fwmask | swmask)))" to "if ((swfw_sync & swmask) && !(swfw_sync & fwmask))". This change breaks some e1000 NIC with a message "ERROR: Unable to read EEPROM!". Signed-off-by: York Sun <yorksun@freescale.com> CC: Marek Vasut <marex@denx.de> CC: Tim Harvey <tharvey@gateworks.com> Acked-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini2014-10-27-1/+1
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| * PowerPC: drop some 74xx_7xx boards and related codeWolfgang Denk2014-10-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file board/Marvell/include/mv_gen_reg.h is incompatible with the GPL (see for example the "MARVELL RESERVES THE RIGHT AT ITS SOLE DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL" clause). As this cannot be fixed, we remove the file and all code that depends on it. Fortunately this only affects some very old boards that have long reached EOL: CPCI750 DB64360 DB64460 p3m750 p3m7448 Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: Roger Meier <r.meier@siemens.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-10-27-268/+150
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| * net: keystone_net: increase PHY auto negotiate timeKhoronzhuk, Ivan2014-10-23-5/+31
| | | | | | | | | | | | | | | | | | | | | | The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time to auto negotiate with SoC's SGMII port. It can take about 3 sec to up the PHY after reset, so add code to expose sgmii auto negotiation waiting process. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: add Keystone2 K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+5
| | | | | | | | | | | | | | | | | | The Keystone2 Edison SoC uses the same keystone net driver. This patch adds opportunity to use it by K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_serdes: add keystone K2E SoC supportKhoronzhuk, Ivan2014-10-23-0/+6
| | | | | | | | | | | | | | | | | | Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov <vitalya@ti.com> Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: use general get link functionKhoronzhuk, Ivan2014-10-23-45/+5
| | | | | | | | | | | | | | | | | | | | | | | | The phy framework has function to get link, so use it instead of own implementation. There is no reason to check SGMII link while sending each packet, phy link is enough. Check SGMII link only while ethernet open. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: register eth PHYs on MDIO busKhoronzhuk, Ivan2014-10-23-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: register MDIO busKhoronzhuk, Ivan2014-10-23-38/+55
| | | | | | | | | | | | | | | | | | | | | | | | Currently MDIO framework is not used to configure Ethernet PHY. As result some of already implemented functions are duplicated. So register MDIO bus in order to use it. On that stage it's just registered, it'll be used as we start to use PHY framework. Use mdio bus read/write/reset functions in the driver. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: use mdio_reset functionKhoronzhuk, Ivan2014-10-23-14/+2
| | | | | | | | | | | | | | | | Don't use mdio_enable twice while eth open. Also rename it to keystone2_mdio_reset as more appropriate name. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: phy: print a number of phy that is not foundKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * soc: keystone_serdes: generalize to be used by other sub systemsHao Zhang2014-10-23-1/+14
| | | | | | | | | | | | | | | | | | | | SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * soc: keystone_serdes: create a separate SGMII SerDes driverKhoronzhuk, Ivan2014-10-23-138/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: remove redundant code from keystone_net.cKhoronzhuk, Ivan2014-10-23-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unused tx_send_loop variable. Removes duplicated get_link_status() call from the keystone2_eth_send_packet(). The emac_gigabit_enable() is called at opening Ethernet and there is no need to enable it on sending each packet. So remove that call from keystone2_eth_send_packet() as well. The calling of power/clock up functions are mostly the responsibility of SoC/board code, so move these functions to appropriate place. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: move header file from arch to ti-commonKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * net: keystone_net: remove SoC specific emac_regs structureHao Zhang2014-10-23-5/+3
| | | | | | | | | | | | | | | | | | | | This patch removes K2HK SOC specifc emac_regs structure, it uses soc specific register offset to keep the network driver common across all the Keystone II EVMs. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * dma: keystone_nav: generalize driver usageKhoronzhuk, Ivan2014-10-23-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * dma: keystone_nav: move keystone_nav driver to driver/dma/Khoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | net: davince: add missing includeJeroen Hofstee2014-10-25-0/+1
| | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | net: fec_mxc: make local functions staticJeroen Hofstee2014-10-25-3/+5
| | | | | | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | net: phy: fix warnings with W=1Jeroen Hofstee2014-10-25-5/+2
| | | | | | | | | | | | | | | | get_phy_id is marked weak but has no protype nor a strong version, just make it static. Use __weak for board_phy_config. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* | net: mvneta.c: Add support for the ethernet controller of the Marvell Armada ↵Stefan Roese2014-10-23-0/+1654
| | | | | | | | | | | | | | | | | | | | | | | | | | | | XP SoC This patch adds support for the NETA ethernet controller which is integrated in the Marvell Armada XP SoC's. This port is based on the Linux driver which has been stripped of the in U-Boot unused portions. Tested on the Marvell MV78460 eval board db-78460-bp. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Tested-by: Luka Perkov <luka@openwrt.org>
* | arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
|/ | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-27/+26
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| * net: dwc: Make the cache handling less crypticMarek Vasut2014-10-06-25/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
| * net: dwc: Fix cache alignment issuesMarek Vasut2014-10-06-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de>
| * net: phy: Cleanup drivers/net/phy/micrel.cPavel Machek2014-10-06-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Chin Liang See <clsee@altera.com>
* | macb: simplify gmac initialisationAndreas Bießmann2014-10-10-17/+8
|/ | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Bo Shen <voice.shen@atmel.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-26-2/+0
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| * board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* | kconfig: add blank Kconfig filesMasahiro Yamada2014-09-24-0/+0
| | | | | | | | | | | | | | | | This would be useful to start moving various config options. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | e1000: fix no nvm buildMarcel Ziswiler2014-09-24-0/+2
|/ | | | | | | | | | | Fix the following build error in case CONFIG_E1000_NO_NVM is enabled: CC drivers/net/e1000.o drivers/net/e1000.c: In function ‘e1000_initialize’: drivers/net/e1000.c:5365:5: error: ‘struct e1000_hw’ has no member named ‘eeprom_semaphore_present’ make[1]: *** [drivers/net/e1000.o] Error 1 make: *** [drivers/net] Error 2 Acked-by: Marek Vasut <marex@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-17-5/+37
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| * net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | | | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* | rtl8169: Defer network packet processingThierry Reding2014-09-16-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When network protocol errors occur (such as a file not being found on a TFTP server), the processing done by the NetReceive() function will end up calling the driver's .halt() implementation. However, after that the device no longer has access to the memory buffers and will cause errors such as this in the rtl_recv() function when trying to hand descriptors back to the device: pci_hose_bus_to_phys: invalid physical address This can be fixed by deferring processing of network packets until the descriptors have been handed back. That way rtl_halt() tearing down network buffers is not going to prevent access to the buffers. Reported-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | openrisc: Fix a few type cast related warningsVasili Galka2014-09-15-4/+4
| | | | | | | | | | | | | | | | | | | | | | Use size_t type for positive offsets instead of the loff_t type. The later is defined as long long, which is larger than the pointer type on OpenRISC architecture and therefore the following warning was generated: "warning: cast to pointer from integer of different size" Signed-off-by: Vasili Galka <vvv444@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-09-12-20/+15
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| * keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan2014-09-04-20/+15
| | | | | | | | | | | | | | | | There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
* | ls102xa: etsec: Add etsec support for LS102xAAlison Wang2014-09-08-0/+7
| | | | | | | | | | | | | | | | | | This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: mdio: Use mb() to be compatible for both ARM and PowerPCAlison Wang2014-09-08-3/+6
| | | | | | | | | | | | | | Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil2014-09-08-5/+2
|/ | | | | | | | | | | | | | | fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* arm: bcm281xx: net: Add Ethernet DriverJiandong Zheng2014-08-30-0/+1535
| | | | | | | | | | | The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom SoC(s) and: - supports multiple MAC blocks, - provides support for the Broadcom GMAC. This driver requires MII and PHYLIB. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* net: cpsw: am335x: Drop constant link checking from rx/tx path'sStefan Roese2014-08-28-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected to the CPSW MAC) that the network performance in U-Boot is quite poor. Only when the transfer is started without a cable connected, and the cable is plugged after the first timeout "T" occured, an increased in performance can be seen. Debugging has revealed, that the cpsw driver has constant link checking builtin into the rx and tx functions. This results in the bad performance and seems to be unnecessary. The link has already been checked in the init function, before the transfer is started. This usually is sufficient. BTW: I have seen no other network driver in U-Boot so far, that constantly checks for link in the rx / tx functions. The performance numbers on the DXR2 board are: 0.56 MiB/s cpsw_check_link() in rx and tx path 0.87 MiB/s cpsw_check_link() only in tx path 1.0 MiB/s cpsw_check_link() only in rx path 2.7 MiB/s no cpsw_check_link() in rx and tx path So with this patch the network performance on DXR2 increases from 0.56 to 2.7 MiB/s (nearly 5 times as fast). Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Samuel Egli <samuel.egli@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
* e1000: add i210 supportMarek Vasut2014-08-21-27/+180
| | | | | | | Add i210 support to the e1000 driver. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* e1000: Implement dcache supportMarek Vasut2014-08-21-22/+49
| | | | | | | | Implement proper support for cache flushing and invalidation into the Intel e1000 NIC driver. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* drivers: net: remove dead driversMasahiro Yamada2014-08-21-459/+0
| | | | | | | | | | The following configs are not defined at all: - CONFIG_INCA_IP_SWITCH - CONFIG_PBL2800_ETHER - CONFIG_PHY_ICPLUS Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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