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* net: gem: Add OF initialization supportMichal Simek2014-03-04-0/+42
| | | | | | Gem can be directly initialized from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: emaclite: Fix OF initializationMichal Simek2014-03-04-8/+9
| | | | | | | | - Add xilinx_emaclite_of_init to netdev.h - Remove global data pointer from the driver - Add better handling for error state. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-0/+1
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * ar8031/8033/phy:enable autonegotiation for ar8031/8033Zhao Qiang2014-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | SMC91111: Fix compilation warningsBhupesh Sharma2014-02-21-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following warning messages coming out of 'drivers/net/smc91111.h' when compiled for 'vexpress_aemv8a': warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Currently this issue seems to surface when SMSC is compiled for 64-bit ARMv8 platforms, so the change is protected under CONFIG_ARM64, so that it doesn't break other existing platforms. In addition this patch tries to fix some checkpatch errors and warnings (others related to camel-casing and volatile usage will be addressed by a later patch). This fix has been tested on both ARMv8 foundation model v1 and v2. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-02-20-65947/+17
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| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-20-1/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
| * \ \ Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-2/+6
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| | * \ \ Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-02-11-167/+9
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| | * | | | NET: fec_mxc: fix MDIO clock prescaler calculationMarkus Niebel2014-02-11-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prescaler value for MDC is calculated wrong for MX6S. Implement the same logic as linux here which handles ENET_MAC different then original FEC. Tested on a custom board with i.MX6S and 100MBit PHY Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
| * | | | | net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2014-02-19-65938/+0
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| | * | | | ARM: NET: Remove the IXP NPE ethernet driverMarek Vasut2014-02-06-65938/+0
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is no longer used, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michael Schwingen <michael@schwingen.org> Cc: Tom Rini <trini@ti.com>
* | | | | blackfin: Add <asm/clock.h> to numerous driversTom Rini2014-02-20-0/+1
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With d6a320d we moved some clock externs out of blackfin_local.h and into clock.h but now need to include <asm/clock.h> in more drivers to avoid warnings. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Tom Rini <trini@ti.com>
* | | | kbuild: use Linux Kernel build scriptsMasahiro Yamada2014-02-19-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we are ready to switch over to real Kbuild. This commit disables temporary scripts: scripts/{Makefile.build.tmp, Makefile.host.tmp} and enables real Kbuild scripts: scripts/{Makefile.build,Makefile.host,Makefile.lib}. This switch is triggered by the line in scripts/Kbuild.include -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj We need to adjust some build scripts for U-Boot. But smaller amount of modification is preferable. Additionally, we need to fix compiler flags which are locally added or removed. In Kbuild, it is not allowed to change CFLAGS locally. Instead, ccflags-y, asflags-y, cppflags-y, CFLAGS_$(basetarget).o, CFLAGS_REMOVE_$(basetarget).o are prepared for that purpose. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Gerhard Sittig <gsi@denx.de>
* | | | net, phy: atheros ar803x bugHeiko Schocher2014-02-19-1/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* | | net/designware: make driver compatible with data cacheAlexey Brodkin2014-02-07-3/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | net/designware - switch driver to phylib usageAlexey Brodkin2014-02-07-327/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | net/designware: add explicit reset of {tx|rx}_currdescnumAlexey Brodkin2014-02-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Driver "init" function might be called multiple times. On every "init" Tx/Rx buffer descriptors are initialized: "descs_init" -> "{tx|rx}_descs_init". In its turn those init functions set MAC's "{tx|rx}desclistaddr" to point on the first buffer descriptor in the list. So CPU to start operation from the first buffer descriptor as well after every "init" we have to reset "{tx|rx}_currdescnum". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | blackfin: Initialize the EMAC VLAN with proper default valueAaron Wu2014-02-07-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot. Signed-off-by: Aaron Wu <Aaron.Wu@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | Merge branch 'net' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-02-04-0/+9
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| * | | net: axi_emac: Check if phy was correctly detectedMichal Simek2014-02-04-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | net: gem: Check if phy was correctly detectedMichal Simek2014-01-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-0/+56
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* | | drivers: delete unused header filesMasahiro Yamada2014-01-24-109/+0
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90fShengzhou Liu2014-01-21-52/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'. When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | powerpc/t2080qds: some update for t2080qdsShengzhou Liu2014-01-21-4/+6
|/ / | | | | | | | | | | | | | | | | | | - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net: phy: atheros: Fix the masks for AR8031/8035Fabio Estevam2014-01-14-2/+2
|/ | | | | | | | | | | | | Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-01-10-78/+99
|\ | | | | | | | | | | | | | | | | | | Bringing in the MMC tree means that CONFIG_BOUNCE_BUFFER needed to be added to include/configs/exynos5-dt.h now. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2014-01-06-78/+99
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: include/micrel.h The conflict above was trivial, caused by four lines being added in both branches with different whitepace.
| | * Net: FEC: Fix huge memory leakMarek Vasut2013-11-21-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | | net: sh-eth: add support for SH7753Yoshihiro Shimoda2013-12-18-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | SH7753 has two fast ethernet controllers and two gigabit ethernet controllers. It is similar to SH7757. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | net/fman: add ft_fixup_xgec to support 3rd and 4th 10GECShengzhou Liu2013-12-11-1/+52
|/ / | | | | | | | | | | | | | | | | As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC. So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4. Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-332/+744
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * \ Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-6/+119
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| | * | powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| | * | net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-6/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2013-11-25-193/+473
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| | * | | net: rtl8169: Add support for RTL8168d/8111dThierry Reding2013-11-22-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is compatible with the existing driver, except that it uses BAR2 instead of BAR1 for the I/O memory region. Using this patch I can use the PCIe ethernet interface on the CompuLab Trimslice to boot from the network. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276477
| | * | | net: rtl8169: Improve cache maintenanceThierry Reding2013-11-22-8/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of directly calling the low-level invalidate_dcache_range() and flush_cache() functions, provide thin wrappers that take into account alignment requirements. While at it, fix a case where the cache was flushed but should have been invalidated, two cases where the buffer data was flushed instead of the descriptor and a missing cache invalidation before reading the packet data that the NIC just wrote to memory. Signed-off-by: Thierry Reding <treding@nvidia.com> Patch: 276474
| | * | | net: zynq_gem: Add d-cache supportSrikanth Thokala2013-11-22-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * | | phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| | * | | phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
| | * | | net: dm9000: random mac address supportAndrew Ruder2013-11-22-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an unprogrammed EEPROM is attached to a dm9000, the dm9000 will come up with a invalid MAC address of ff:ff:ff:ff:ff:ff. Add code that gets enabled if CONFIG_RANDOM_MACADDR is enabled that generates a random (and valid) locally administered MAC address that allows the system to network boot until a real MAC address can be configured. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
| | * | | drivers/net/e1000: Introduce CONFIG_E1000_NO_NVMRojhalat Ibrahim2013-11-22-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The e1000 driver expects to always have some kind of non-volatile memory attached directly to the ethernet controller chip. This means that I would have to add an additional separate flash chip to my custom board just to store essentially the MAC address. Since I don't want to do that, this patch introduces a new config option CONFIG_E1000_NO_NVM. If defined it disables all accesses to the NVM. I have tested the patch with a 82574 controller. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
| | * | | net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
| | * | | net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
| | * | | net: tsec: Fix mac addr setup portability, cleanupClaudiu Manoil2013-11-22-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the 32-bit memory access that is not "endianess safe", i.e. not giving the desired byte layout for LE cpus: tempval = *((uint *) (tmpbuf + 4)), where 'char tmpbuf[]'. Free the stack from rendundant local vars: tmpbuf[] and i. Use a portable type (u32) for the 32bit tsec register value holder: tempval. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
| | * | | net: tsec: Use portable regs type (uint->u32)Claudiu Manoil2013-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use cross arch portable u32 instead of uint for the tsec registers. Remove the typedefs for the register struct definitions in the process. Fix long lines. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
generated by cgit v1.1 at 2024-12-20 22:43:34 +0000