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* Move console definitions into a new console.h fileSimon Glass2015-11-19-0/+4
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: zynq: Fix MDC setting for zynqMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Remove unused MDCCLKDIV2 macroMichal Simek2015-11-19-1/+0
| | | | | | | Driver cleanup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix mdc clock division setting for 100Mbit/sMichal Simek2015-11-19-2/+2
| | | | | | | | | | | Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Wait till packet is sentMichal Simek2015-11-19-1/+32
| | | | | | Wait till BD is processed to ensure that packet was sent successfully. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Disable secondary queuesEdgar E. Iglesias2015-11-19-0/+26
| | | | | | | | | | | | Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Add dummy packet to fix packet duplication issueMichal Simek2015-11-19-2/+8
| | | | | | | | | Target is duplicating packets. IP prefetches another BD and process it when the first one is sent. Adding one dummy BD to the chain fix the problem with packet duplication. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Do not report TX underrunMichal Simek2015-11-19-2/+0
| | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Setup BD when structures are filledMichal Simek2015-11-19-3/+3
| | | | | | | Fix incorrect sequence in BD handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Allocate BD_SPACE in connection to RX_BUFMichal Simek2015-11-19-1/+1
| | | | | | | | | BD_SEPRN_SPACE should not have hard coded value and it will be calculated based on the number of buffer descriptors that we would like to use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix clearing statisticMichal Simek2015-11-19-4/+3
| | | | | | | | Previous loop was completely bogus. Iterration should go just over statistic counters. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Extend register description with offsetsMichal Simek2015-11-19-15/+15
| | | | | | | Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add support for different PHY interface typesMichal Simek2015-11-19-1/+8
| | | | | | | | | | | | | MII is setup by default for all cases. The most of boards are using RGMII but PHY drivers are not doing any specific setting that's why MII setting was working fine. With TI DP83867 is necessary to setup paramaters based on interface type. Use one setting per board for it which is something what will be removed when driver is moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add debug message to phyread/phywriteMichal Simek2015-11-19-1/+12
| | | | | | | Add debug messages to phyread/write to help with PHY debug. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Add support for Texas Instruments DP83867Edgar E. Iglesias2015-11-19-0/+204
| | | | | | | | | Code is taken from Linux kernel driver (v4.2). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* altera_tse: change ioremap to map_physmemThomas Chou2015-11-18-1/+1
| | | | | | | Change ioremap() to map_physmem(), as it is more used in u-boot. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* sparc: leon3: Moved GRLIB core header files to common include/grlib directoryDaniel Hellstrom2015-11-13-1/+1
| | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* sparc: leon3: Reimplemented AMBA Plug&Play scanning routines.Daniel Hellstrom2015-11-13-2/+13
| | | | Signed-off-by: Daniel Hellstrom <daniel@gaisler.com>
* pengwyn: nand and ethernet fixesVincent BENOIT2015-11-12-2/+43
| | | | | | -> Add National instrument ethernet transceiver configuration used (DP83848) -> Change cpsw slave phy address -> modify nand configuration to use the correct ECC and correct nand features
* driver: net: Fix pointer conversion warnings for xilinx_zynqmp_epPrabhakar Kushwaha2015-11-12-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below warnings happening for xilinx_zynqmp_ep_defconfig drivers/net/zynq_gem.c: In function ‘zynq_gem_init’: drivers/net/zynq_gem.c:330:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] ((u32)(priv->rxbuffers) + ^ In file included from drivers/net/zynq_gem.c:19:0: drivers/net/zynq_gem.c:336:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] writel((u32)priv->rx_bd, &regs->rxqbase); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_send’: drivers/net/zynq_gem.c:399:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] writel((u32)priv->tx_bd, &regs->txqbase); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/net/zynq_gem.c:404:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] priv->tx_bd->addr = (u32)ptr; ^ drivers/net/zynq_gem.c:409:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] addr = (u32) ptr; ^ drivers/net/zynq_gem.c:414:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] addr = (u32)priv->rxbuffers; ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_recv’: drivers/net/zynq_gem.c:454:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] net_process_received_packet((u8 *)addr, frame_len); ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_initialize’: drivers/net/zynq_gem.c:533:35: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); ^ drivers/net/zynq_gem.c:533:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* net: altera_tse: add mSG-DMA supportThomas Chou2015-11-12-0/+191
| | | | | | | | | | | The Modular Scatter-Gather DMA core is a new DMA core to work with the Altera Triple-Speed Ethernet MegaCore. It replaces the legacy Scatter-Gather Direct Memory Access (SG-DMA) controller core. Please find details on the "Embedded Peripherals IP User Guide" of Altera. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* net: altera_tse: add priv ops to prepare msgdma supportThomas Chou2015-11-12-25/+81
| | | | | | | | Add priv ops to prepare msgdma support. These ops are dma type specific. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* net: altera_tse: wait sgdma in altera_tse_recvThomas Chou2015-11-12-1/+1
| | | | | | | | Move the sgdma wait from free_pkt to recv. This is the proper place to wait recv sgdma done. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* net: altera_tse: factor out stop mac funcThomas Chou2015-11-12-15/+21
| | | | | | | Factor out the stop mac function to prepare msgdma support. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de>
* net: altera_tse: get numbers of fdt address and size cellsThomas Chou2015-11-06-6/+8
| | | | | | | | | Get numbers of fdt address and size cells in altera_tse_probe(), thereby remove the assumption of one address cell and one size cell. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: altera_tse: use BIT macroThomas Chou2015-11-06-15/+15
| | | | | | | | | | | | | | Replace numerical bit shift with BIT macro in altera_tse :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: altera_tse: remove the useless parenthesisThomas Chou2015-11-06-15/+15
| | | | | | | | | Remove the useless parenthesis. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: altera_tse: fix packed and aligned attributeThomas Chou2015-11-06-1/+1
| | | | | | | | | | | | | | | | | | Fix packed and aligned attribute warnings. WARNING: __packed is preferred over __attribute__((packed)) #14: FILE: drivers/net/altera_tse.h:14: +#define __packed_1_ __attribute__ ((packed, aligned(1))) WARNING: __aligned(size) is preferred over __attribute__((aligned(size))) #14: FILE: drivers/net/altera_tse.h:14: +#define __packed_1_ __attribute__ ((packed, aligned(1))) Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: altera_tse: use data type u32 for regs and descThomas Chou2015-11-06-60/+60
| | | | | | | | | | Use data type u32/u16/u8 for regs and desc, as it is more portable. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: altera_tse: remove unused macro and regs defThomas Chou2015-11-06-101/+3
| | | | | | | | | Remove unused macro and regs def. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Chin Liang See <clsee@altera.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* video: Drop DEV_FLAGS_SYSTEM flagBin Meng2015-11-05-1/+1
| | | | | | DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-10-30-110/+283
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| * armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-2/+128
| | | | | | | | | | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-29-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Add QSGMII PCS initShaohui Xie2015-10-29-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | QSGMII PCS needed to be programmed same as SGMII PCS, and there are four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared port 0's MDIO controller, so when programming port 0, we continue to program other three ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: Move some header files to include/Shaohui Xie2015-10-29-6/+6
| | | | | | | | | | | | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net: fm: bug fix when CONFIG_PHYLIB not definedShaohui Xie2015-10-29-1/+7
| | | | | | | | | | | | | | | | codes related to phylib operations should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Make the return value logic consistent with conventionHou Zhiqiang2015-10-29-24/+36
| | | | | | | | | | | | | | | | | | | | In convention, the '0' is a normal return value indicating there isn't an error. While some functions of FMan IM driver treat '0' as an error return value. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Add support for 64-bit platformsHou Zhiqiang2015-10-29-33/+60
| | | | | | | | | | | | | | | | | | | | | | | | The FMan IM driver is developed for 32-bit platfroms and isn't friendly to 64-bit platforms, so do the minimal refactor: 1. Refine the MURAM management and access. 2. Correct the initialization and operations for QDs and BDs. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * net/fm: Fix the endian issue to support both endianness platformsHou Zhiqiang2015-10-29-38/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Frame Manager(FMan) is a big-endian peripheral, so the registers, internal MURAM and BDs, which are allocated in main memory and used to communication between core and FMan, should be accessed in big-endian. The big-endian platforms can access them directly as the code implemented so far, while for the little-endian platforms it need to swap the byte-order. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * driver: net: ldpaa_eth: Set MAC address during interface openPrabhakar Kushwaha2015-10-29-12/+3
| | | | | | | | | | | | | | | | | | | | Currently ldpaa ethernet driver rely on DPL file to statically configure mac address for the DPNIs. It is not a correct approach. Add support setting MAC address from env variable or Random MAC address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net: pch_gbe: Add driver remove supportBin Meng2015-10-29-0/+12
| | | | | | | | | | | | | | | | | | | | In pch_gbe_probe(), some additional resources are allocated (eg: mdio, phy). We should free these in the driver remove phase. Add pch_gbe_remove() to clean it up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: designware: Add driver remove supportBin Meng2015-10-29-0/+12
| | | | | | | | | | | | | | | | | | In designware_eth_probe(), some additional resources are allocated (eg: mdio, phy). We should free these in the driver remove phase. Add designware_eth_remove() to clean it up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | net: phy: Test previous phydev->dev against new mac devBin Meng2015-10-29-1/+1
| | | | | | | | | | | | | | | | | | | | In phy_connect_dev(), if the phy device has an accociated mac device before, a warning message will be printed. But we should test the old device against the new one, if they are actually the same one, don't print the warning message. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: Change to print all phys that are not foundBin Meng2015-10-29-1/+8
| | | | | | | | | | | | | | | | | | | | | | In get_phy_device_by_mask(), when no phy is found, currently we only print a message to show the first phy address that is not found. But this is not always the case as multiple phys can be specified by phy_mask. Change to print all phys that are not found, and to reduce the console boot log, change to use 'debug' instead of 'printf'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: Don't create phy device when there is no phyBin Meng2015-10-29-1/+2
| | | | | | | | | | | | | | | | In get_phy_device_by_mask(), when no phy is found, we should not create any phy device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: micrel: disable NAND-tree for KSZ8051Sylvain Rochet2015-10-29-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND-tree is used to check wiring between MAC and PHY using NAND gates on the PHY side, hence the name. NAND-tree initial status is latched at reset by probing the IRQ pin. However some devices are sharing the PHY IRQ pin with other peripherals such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000 display module, therefore they are switching the PHY in NAND-tree test mode depending on the current IRQ line status at reset. This patch ensure PHY is not in NAND-tree test mode only for the Micrel KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I doubt they are used on such weird hardware design. Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: rtl8169: Build warning fixes for 64-bitStephen Warren2015-10-29-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Casting from dev->priv to pci_dev_t changes the value's size on a 64-bit system. This causes the compiler to complain about casting a pointer to an integer of a different (smaller) size. To avoid this, cast to an integer of matching size first, then perform an int->int cast to perform the size change. This signals explicitly that we do want to change the size, and avoids the compiler warning. This is legitimate since we know the pointer actually stores a small integer, not a pointer value. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: micrel: add support for KSZ8021RNL & KSZ8031RNLSylvain Lemieux2015-10-29-0/+11
|/ | | | | | | This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: convert altera_tse to driver model and phylibThomas Chou2015-10-23-1047/+382
| | | | | | | | Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
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