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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-1501/+109
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* net: phy: Set SUPPORTED_1000baseX_Half flag in ESTATUS_1000_XHALF caseFabio Estevam2013-07-19-1/+1
| | | | | | | | | | | | | Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the checking for ESTATUS_1000_XHALF, but it incorrectly sets the SUPPORTED_1000baseX_Full flag in this case. Set the SUPPORTED_1000baseX_Half flag instead. Acked-by: Charles Coldwell <coldwell@gmail.com> Reviewed-By: Sascha Silbe <t-uboot@infra-silbe.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* phy: fix 10/100Mbps operation on 1Gbps-capable linksSascha Silbe2013-07-19-1/+9
| | | | | | | | | | | | | | | | | de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a check for the extended status register in order to support 1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since Extended Status only indicates what the PHY (i.e. the local side) is capable of, this broke communication with non-1Gbps peers. Only check the extended status if the 1000BASE-T registers are actually missing so we don't end up setting speed to 1Gbps even though the previous test (for the combination of local and peer support for 1Gbps) already indicated we can't do 1Gbps with the current peer. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-07-12-1/+22
|\ | | | | | | | | | | | | | | | | | | Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and serial. Conflicts: arch/arm/dts/exynos5250.dtsi Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-07-12-1/+22
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| | * net: fec: Avoid MX28 bus sync issueMarek Vasut2013-07-12-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX28 multi-layer AHB bus can be too slow and trigger the FEC DMA too early, before all the data hit the DRAM. This patch ensures the data are written in the RAM before the DMA starts. Please see the comment in the patch for full details. This patch was produced with an amazing help from Albert Aribaud, who pointed out it can possibly be such a bus synchronisation issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
| | * net: fec: Remove bogus flush_dcache_range() callMarek Vasut2013-07-12-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove incorrectly called and duplicate flush_dcache_range() call from fec_mxc driver. The call is not needed, since the caches are already flushed in fec_tbd_init(), moreover the second argument should be the ending address, not size. Signed-off-by: Marek Vasut <marex@denx.de> Reported-by: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* | | phylib: add atheros ar803x phyHeiko Schocher2013-06-24-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* | | phylib: add natsemi dp83630 phyHeiko Schocher2013-06-24-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | add natsemi dp83630 phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* | | net: update FTGMAC100 for MMU/D-cache supportKuo-Jung Su2013-06-24-21/+49
| | | | | | | | | | | | | | | | | | Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Tom Rini <trini@ti.com>
* | | net: add Faraday FTMAC110 10/100Mbps ethernet supportKuo-Jung Su2013-06-24-0/+651
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Faraday FTMAC110 10/100Mbps supports half-word data transfer for Linux. However it has a weird DMA alignment issue: (1) Tx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: O.K (2) Rx DMA Buffer Address: 1 bytes aligned: Invalid 2 bytes aligned: O.K 4 bytes aligned: Invalid!!! Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
* | | net: phy: supplement support for Micrel's KSZ9031SARTRE Leo2013-06-24-1/+35
| | | | | | | | | | | | | | | | | | Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
* | | net: macb: add support for gigabit MACBo Shen2013-06-24-38/+168
| | | | | | | | | | | | | | | | | | | | | Add gigabit MAC support in macb driver - using IP version to distinguish whether MAC is GMAC Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | | net: macb: using phylib to configure phy deviceBo Shen2013-06-24-2/+14
| | | | | | | | | | | | | | | | | | using phylib to configure phy device in macb driver Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | | net: macb: using AT91FAMILY replace #ifdeferryBo Shen2013-06-24-8/+2
| | | | | | | | | | | | | | | | | | | | | Using CONFIG_AT91FAMILY replace #ifdeferry for atmel SoC Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | net: ks8851_mll: add ethernet supportRoberto Cerati2013-06-24-0/+1003
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The device interface is 16 bits wide. All the available packets are read from the incoming fifo. Signed-off-by: Roberto Cerati <roberto.cerati@bticino.it> Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> [voice.shen@atmel.com: address comments from review results] [voice.shen@atmel.com: clean up for submit] Signed-off-by: Bo Shen <voice.shen@atmel.com> Tested-by: Raffaele Recalcati <raffaele.recalcati@bticino.it>
* | | phylib: Add Atheros AR8035 GETH PHY supportXie Xiaobo2013-06-24-1/+33
| | | | | | | | | | | | Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* | | add support for Xilinx 1000BASE-X phy (GTX)Charles Coldwell2013-06-24-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 39695029bc15041c809df3db4ba19bd729c447fa Author: Charles Coldwell <coldwell@ll.mit.edu> Date: Tue Feb 19 08:27:33 2013 -0500 Changes to support the Xilinx 1000BASE-X phy (GTX/MGT) Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
* | | PHY: micrel.c: add support for KSZ9031David Andrey2013-06-24-27/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Micrel PHY KSZ9031 in phylib, including small rework for KSZ9021 to avoid code duplication Signed-off-by: David Andrey <david.andrey@netmodule.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Joe Herschberger <joe.hershberger@gmail.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* | | net: Fix build regression in macb.cJoe Hershberger2013-06-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The added weak symbol must not be static. This was introduced in 416ce623fbad51af57660346ebb6f7befb88b3c9 Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | | net/macb: Add arch specific routine to get mdio controlShiraz Hashim2013-06-24-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPEAr310 and SPEAr320 Ethernet interfaces share same MDIO lines to control their respective phys. Currently there is a fixed configuration in which only a particular MAC can use the MDIO lines. Call an arch specific function to take control of specific mdio lines at runtime. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de>
* | | net/designware: Do not select MIIPORT for RGMII interfaceVipin Kumar2013-06-24-1/+3
| | | | | | | | | | | | | | | | | | | | | Do not select MIIPORT for RGMII interface Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de>
* | | NET: mvgbe: add support for DoveSebastian Hesselbarth2013-06-24-0/+9
| | | | | | | | | | | | | | | | | | | | | Marvell Dove also uses mvgbe as ethernet driver, therefore add support for Dove to reuse the current driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | | NET: mvgbe: add phylib supportSebastian Hesselbarth2013-06-24-4/+65
| | | | | | | | | | | | | | | | | | This add phylib support to the Marvell GBE driver. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | | NET: phy: add 88E1310 PHY initializationSebastian Hesselbarth2013-06-24-0/+48
| | | | | | | | | | | | | | | | | | This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | | net: add ICPlus PHY driverYegor Yefremov2013-06-24-0/+98
| | | | | | | | | | | | | | | | | | | | | The driver code was taken from Linux kernel source: drivers/net/phy/icplus.c Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | | phy: export genphy_parse_link()Yegor Yefremov2013-06-24-1/+1
| | | | | | | | | | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | | net: Add sunxi (Allwinner) wemac driverHenrik Nordström2013-06-24-0/+534
|/ / | | | | | | | | | | | | | | | | | | This patch adds support for the WEMAC, the ethernet controller included in the Allwinner A10 SoC. It will get used in the upcoming A10 board support. From: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-08-3/+1
|\ \ | |/ | | | | | | Conflicts: drivers/serial/Makefile
| * net: fec_mxc: Add support for Vybrid VF610Alison Wang2013-06-03-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FEC support for Vybrid VF610 platform. In function fec_open(), RCR register is only set as RGMII mode. But RCR register should be set as RMII mode for VF610 platform. This configuration is already done in fec_reg_setup(), so this piece of code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-12/+133
|\ \ | |/ |/| | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/phy: fix select line for TN80xxShaohui Xie2013-05-24-2/+14
| | | | | | | | | | | | | | | | | | | | TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxTom Rini2013-05-15-4/+113
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| | * net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * net/fm: fixup ethernet for mEMACShengzhou Liu2013-05-14-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | - set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-14-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | smc911x: fix the timeout detectionMasahiro Yamada2013-05-15-2/+2
| | | | | | | | | | | | | | | | | | | | | If timeout is occurred at the while loop above, the value of 'timeout' is -1, not 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | blackfin: The buf variable in bfin_mac.c is not used and produces warning,Marek Vasut2013-05-13-2/+0
| |/ | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-0/+120
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| * | phy: add support for ET1011C physMatt Porter2013-05-10-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | cpsw: add support for TI814x slave_regs differencesMatt Porter2013-05-10-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | TI814x's version 1 CPSW has a different slave_regs layout. Add support for the differing registers. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-0/+17
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| * fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+17
| | | | | | | | | | | | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | net: gem: Add support for phy autodetectionMichal Simek2013-04-30-0/+51
| | | | | | | | | | | | | | Autodetect phy if phyaddress is setup to -1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Preserve clk on emio interfaceDavid Andrey2013-04-30-3/+9
| | | | | | | | | | | | | | | | | | | | | | Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL if the Ethernet interface is connect on EMIO Do not enable emio for this standard board configuration for now. Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Pass phy address to initDavid Andrey2013-04-30-6/+2
| | | | | | | | | | | | | | | | | | Pass the PHY address to the driver init to allow parallel use of both interfaces Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-15/+38
| | | | | | | | | | | | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Do not initialize BDs againMichal Simek2013-04-30-39/+47
| | | | | | | | | | | | | | | | | | | | | | BDs can be correctly setup just once and init function performs only phy autodetection and enabling RX/TX. RX/TX are disabled in halt function. This patch solves the problem with repeatable tftp transfers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
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