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* treewide: replace #include <asm-generic/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | | | | Now, include/linux/errno.h is a wrapper of <asm-generic/errno.h>. Replace all include directives for <asm-generic/errno.h> with <linux/errno.h>. <asm-generic/...> is supposed to be included from <asm/...> when arch-headers fall back into generic implementation. Generally, they should not be directly included from .c files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Add drivers/usb/host/xhci-rockchip.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-5/+9
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * net: zynq_gem: Add the passing of the phy-handle nodeDan Murphy2016-05-24-5/+10
| | | | | | | | | | | | | | | | | | | | Add the ability to pass the phy-handle node offset to the phy driver. This allows the phy driver to access the DT subnode's data and parse accordingly. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | phy: Wire return value from phy_config()Michal Simek2016-05-24-2/+1
| | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: xilinx: Handle error value from phy_startup()Michal Simek2016-05-24-1/+4
|/ | | | | | | Handle error returned by phy_startup() properly. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* net: zynq_gem: Add SGMII support for zynqMPSiva Durga Prasad Paladugu2016-04-04-2/+11
| | | | | | | | | PCS auto negotaiation bit should be enabled along with SGMII autonegotation enabled in phy. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Return error incase of invalid phy addressSiva Durga Prasad Paladugu2016-04-04-3/+1
| | | | | | | | Return error from probe in case of invalid phy address. This fixes the issue of uboot crash if phy is not detected. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Allow to set the MAC from an EEPROMJoe Hershberger2016-04-04-0/+18
| | | | | | | | | | Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add support for SGMII interfaceSiva Durga Prasad Paladugu2016-04-04-7/+19
| | | | | | | | Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Change MDC setup for arm64Michal Simek2016-01-27-0/+4
| | | | | | | | | MDC setting depends on pclk input clocks which varies across SoC. This driver is used by xilinx zynq and zynqmp SOC. Input clock frequence on silicon is 125MHz where divider 64 put frequency below 2.5MHz requires by spec (125/64=1.95). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Use shared wait_for_bitMateusz Kulikowski2016-01-25-33/+2
| | | | | Use existing library function to poll bit(s). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
* net: gem: Add driver dependencies to PHYLIBMichal Simek2015-12-18-4/+0
| | | | | | | Clear driver dependecies via Kconfig. Remove PHYLIB dependency from the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Separate recv and free_pkt functionsMichal Simek2015-12-18-20/+32
| | | | | | | | Use core to call net_process_received_packet() instead of call inside the driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Fix return value from recvMichal Simek2015-12-18-1/+1
| | | | | | | | recv function should return 0 instead of frame_len not to proceed the same packet again in core. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Setup default phy address to -1Michal Simek2015-12-18-1/+2
| | | | | | | Undefined phy address is -1 not 0. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Enable CTRL+C in wait_for_bitMichal Simek2015-12-07-0/+6
| | | | | | | Enable to break waiting loop at any time. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Read information about interface from DTMichal Simek2015-12-07-8/+12
| | | | | | | Do not set interface via configs. Read information from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* net: gem: Move driver to DMMichal Simek2015-12-07-69/+110
| | | | | | | | | | | | | - Enable DM_ETH by default for Zynq and ZynqMP - Remove board_eth_init code - Change miiphy_read function to return value instead of error code based on DM requirement - Do not enable EMIO DT support by default Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* net: gem: Fix miiphy_read nameMichal Simek2015-12-07-2/+2
| | | | | | | Sync it with write function. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* net: gem: Remove zynq_gem_of_init()Michal Simek2015-12-07-42/+0
| | | | | | | | | This function was used for OF init before DM. Remove this function as the part of move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com>
* net: gem: Enable MDIO bus earlierMichal Simek2015-12-07-5/+9
| | | | | | | Enable access to MDIO before zynq_gem_init is called. It enables read information about phy earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Check if priv->phydev is validMichal Simek2015-12-07-0/+2
| | | | | | | Check return value. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* net: gem: Extract phy init codeMichal Simek2015-12-07-17/+30
| | | | | | | Move phy init code out of zynq_gem_init. DM drivers are normally calling this code from probe function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Remove phydev variableMichal Simek2015-12-07-13/+10
| | | | | | | Resort code to use priv->phydev variable directly. It will simplify move to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Change mii function not to use eth_device structureMichal Simek2015-12-07-13/+19
| | | | | | | | Next step to move driver to driver model. Do not use eth_device structure. Use private structure instead. Add iobase to private structure to store gem iobase. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Change mdio_wait prototype to pass regsMichal Simek2015-12-07-4/+3
| | | | | | | Pass regs instead of dev because this will be chagned by driver model. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Do not continue if phy is not foundMichal Simek2015-12-07-4/+10
| | | | | | | | Add return value for phy detection algorithm to stop init function when phy is not found. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* net: zynq: Fix MDC setting for zynqMichal Simek2015-11-19-1/+1
| | | | | | | | | | | | | Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Remove unused MDCCLKDIV2 macroMichal Simek2015-11-19-1/+0
| | | | | | | Driver cleanup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix mdc clock division setting for 100Mbit/sMichal Simek2015-11-19-2/+2
| | | | | | | | | | | Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Wait till packet is sentMichal Simek2015-11-19-1/+32
| | | | | | Wait till BD is processed to ensure that packet was sent successfully. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Disable secondary queuesEdgar E. Iglesias2015-11-19-0/+26
| | | | | | | | | | | | Zynq has no priority queues. ZynqMP has one priority queue and this change is required to get ethernet working. This patch was not needed on ep108 for uknown reason even it should be used. Tested on Zynq and ZynqMP. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Add dummy packet to fix packet duplication issueMichal Simek2015-11-19-2/+8
| | | | | | | | | Target is duplicating packets. IP prefetches another BD and process it when the first one is sent. Adding one dummy BD to the chain fix the problem with packet duplication. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Do not report TX underrunMichal Simek2015-11-19-2/+0
| | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Setup BD when structures are filledMichal Simek2015-11-19-3/+3
| | | | | | | Fix incorrect sequence in BD handling. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Allocate BD_SPACE in connection to RX_BUFMichal Simek2015-11-19-1/+1
| | | | | | | | | BD_SEPRN_SPACE should not have hard coded value and it will be calculated based on the number of buffer descriptors that we would like to use. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Fix clearing statisticMichal Simek2015-11-19-4/+3
| | | | | | | | Previous loop was completely bogus. Iterration should go just over statistic counters. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Extend register description with offsetsMichal Simek2015-11-19-15/+15
| | | | | | | Extend comments with register offset to help with debuggging. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add support for different PHY interface typesMichal Simek2015-11-19-1/+8
| | | | | | | | | | | | | MII is setup by default for all cases. The most of boards are using RGMII but PHY drivers are not doing any specific setting that's why MII setting was working fine. With TI DP83867 is necessary to setup paramaters based on interface type. Use one setting per board for it which is something what will be removed when driver is moved to DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: zynq: Add debug message to phyread/phywriteMichal Simek2015-11-19-1/+12
| | | | | | | Add debug messages to phyread/write to help with PHY debug. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* driver: net: Fix pointer conversion warnings for xilinx_zynqmp_epPrabhakar Kushwaha2015-11-12-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix below warnings happening for xilinx_zynqmp_ep_defconfig drivers/net/zynq_gem.c: In function ‘zynq_gem_init’: drivers/net/zynq_gem.c:330:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] ((u32)(priv->rxbuffers) + ^ In file included from drivers/net/zynq_gem.c:19:0: drivers/net/zynq_gem.c:336:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] writel((u32)priv->rx_bd, &regs->rxqbase); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_send’: drivers/net/zynq_gem.c:399:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] writel((u32)priv->tx_bd, &regs->txqbase); ^ ./arch/arm/include/asm/io.h:146:34: note: in definition of macro ‘writel’ #define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) ^ drivers/net/zynq_gem.c:404:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] priv->tx_bd->addr = (u32)ptr; ^ drivers/net/zynq_gem.c:409:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] addr = (u32) ptr; ^ drivers/net/zynq_gem.c:414:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] addr = (u32)priv->rxbuffers; ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_recv’: drivers/net/zynq_gem.c:454:31: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] net_process_received_packet((u8 *)addr, frame_len); ^ drivers/net/zynq_gem.c: In function ‘zynq_gem_initialize’: drivers/net/zynq_gem.c:533:35: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); ^ drivers/net/zynq_gem.c:533:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->rx_bd = (struct emac_bd *)((u32)bd_space + BD_SEPRN_SPACE); Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* net: gem: Extend timeout valueMichal Simek2015-07-28-1/+1
| | | | | | Extend time for MDIO. (Because of zed board) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: gem: Setting up WRAP bit for one TX bdMichal Simek2015-07-28-1/+2
| | | | | | | Setting up WRAP bit to indicate that this is the last TX BD in the chain. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynq: gem: Increase the Rx buffer descriptors to 32Siva Durga Prasad Paladugu2015-07-28-1/+1
| | | | | | | | | | | Increase the Rx Buffer descriptors to 32. This will avoid Rx buffer descriptors overflow if more packets were received at one shot before we process the received ones. This fixes the issue of intermittent timeouts during tftp on a 1Gb connection with tftp server running on windows. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: gem: Flush the rx buffers while transmittingSiva Durga Prasad Paladugu2015-07-28-3/+7
| | | | | | | | | Flush and invalidate the rx buffers while sending the tx packet it self as armv8 does flush also while doing invalidation. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* zynqmp: gem: Set data bus width to 64bit for arm64Siva Durga Prasad Paladugu2015-07-28-1/+8
| | | | | | | | Set the data bus width to 64-bit AMBA Databus width in config register. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: gem: Use correct type for castingMichal Simek2015-04-20-1/+2
| | | | | | | Use phys_addr_t which is used in function prototype in system.h. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: cosmetic: Fix var naming net <-> eth driversJoe Hershberger2015-04-18-1/+1
| | | | | | | | | | | | | | | Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: gem: Use phys_addr_t instead of int for addressesMichal Simek2015-01-21-2/+3
| | | | | | | Use phys_addr_t for physical address declaration. It is also unsigned type instead of sign. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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