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path: root/drivers/net/zynq_gem.c
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* net: zynq: Fix sparse warnings in gemMichal Simek2014-05-06-0/+1
| | | | | | | | | | Add missing header. Warnings: drivers/net/zynq_gem.c:491:5: warning: symbol 'zynq_gem_initialize' was not declared. Should it be static? drivers/net/zynq_gem.c:542:5: warning: symbol 'zynq_gem_of_init' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq: Use predefined macros instead of hardcoded valueMichal Simek2014-05-06-1/+2
| | | | | | MII is used by this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Add OF initialization supportMichal Simek2014-03-04-0/+42
| | | | | | Gem can be directly initialized from DTB. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Calculate clock dividers dynamicallySoren Brinkmann2014-02-19-6/+11
| | | | | | | | Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Move RCLK details out of driverSoren Brinkmann2014-02-19-5/+2
| | | | | | | | | The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: gem: Check if phy was correctly detectedMichal Simek2014-01-21-0/+5
| | | | | | | As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: zynq_gem: Add d-cache supportSrikanth Thokala2013-11-22-29/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added d-cache support for zynq_gem.c, Observed a difference of +0.8 MiB/s when downloading a file of size of 3007944Bytes. With d-cache OFF: ---------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 1.3 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) With d-cache ON: --------------- Filename 'uImage'. Load address: 0x800 Loading: ################################################################# ################################################################# ################################################################# ########## 2.1 MiB/s done Bytes transferred = 3007944 (2de5c8 hex) Changes on zynq_gem for d-cache support: - Tx and Rx buffers are cache-aligned - Updated logic for invalidating Rx buffers and flushing Tx buffers. - Tx and Rx BD's are allocated from non-cacheable region. (When BDs are cached, we don't see a consistent link) - Use TX BD status intead of txsr status checks. Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* net: gem: Add support for phy autodetectionMichal Simek2013-04-30-0/+51
| | | | | | | Autodetect phy if phyaddress is setup to -1. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Preserve clk on emio interfaceDavid Andrey2013-04-30-3/+9
| | | | | | | | | | | Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL if the Ethernet interface is connect on EMIO Do not enable emio for this standard board configuration for now. Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Pass phy address to initDavid Andrey2013-04-30-6/+2
| | | | | | | | | Pass the PHY address to the driver init to allow parallel use of both interfaces Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-15/+38
| | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Do not initialize BDs againMichal Simek2013-04-30-39/+47
| | | | | | | | | | | BDs can be correctly setup just once and init function performs only phy autodetection and enabling RX/TX. RX/TX are disabled in halt function. This patch solves the problem with repeatable tftp transfers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Simplify return path in zynq_gem_recvMichal Simek2013-04-30-3/+1
| | | | | | | Remove one return from the code. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: gem: Remove WRAP bit from TX buffer descriptionMichal Simek2013-04-30-2/+1
| | | | | | | | | | | | Removing this bit causes that frame is sent only once. (With wrap big one packet has been sent several times which dramatically decrease throughput) TRM: (Table 16-3: Tx Buffer Descriptor Entry) Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* net: Add driver for Zynq Gem IPMichal Simek2012-09-26-0/+440
Device driver for Zynq Gem IP. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Joe Hershberger <joe.hershberger@gmail.com> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
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