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path: root/drivers/net/tsec.c
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* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-5/+5
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* enable 10/100M at VSC8601 at tsec driverAndre Schwarz2008-10-13-0/+2
| | | | | | | | | Currently VSC8601 doesn't link with 10/100M partners if the EEPROM/Strapping is not set up. Setting the auto-neg register fixes this. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Support for multiple SGMII/TBI interfaces for TSEC ethernetPeter Tyser2008-09-16-3/+5
| | | | | | | | | Fix TBI PHY accesses to use the proper offset in CPU register space. The previous code would incorrectly access the TBI PHY by reading/writing to CPU register space at the same location as would be used to access external PHYs. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Add SGMII support to the tsecAndy Fleming2008-09-02-26/+48
| | | | | | | Adds support for configuring the TBI to talk properly with the SerDes. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-63/+50
| | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* tsec: Move tsec.h to include/Andy Fleming2008-09-02-7/+1
| | | | | | | This is to prepare the way for board code passing in the tsec_info structure Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* PHY: Add support for the M88E1121R Marvell chip.Sergei Poselenov2008-09-02-0/+49
| | | | | | Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* net: Conditional COBJS inclusion of network driversShinya Kuribayashi2008-06-09-3/+0
| | | | | | | Replace COBJS-y with appropriate driver config names. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Add Marvell 88E1118 support for TSECRon Madrid2008-05-23-0/+31
| | | | | Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* drivers/net/tsec.c: Fix typo.Wolfgang Denk2008-05-04-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* TSEC: add config options for VSC8601 RGMII PHYAndre Schwarz2008-05-03-0/+6
| | | | | | | | | | | | | | | | | The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-)
* Add Vitesse 8601 support to TSEC driverTor Krill2008-03-31-0/+30
| | | | | | | | | Add phy_info for Vitesse VSC8601. Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation. Signed-off-by: Tor Krill <tor@excito.com> Reviewed-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* tsec: fix link detection for the RTL8211B PHYAnton Vorontsov2008-03-25-2/+3
| | | | | | | | | | | RTL8211B sets link state register after autonegotiation complete, so with bootdelay=0 RTL8211B will report lack of the link. To fix this, we should wait for aneg to complete, even if the link is currently down. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* TSEC: Add the support for RealTek RTL8211B PHYDave Liu2008-01-16-0/+85
| | | | | | | | Add the support of RealTek RTL8211B PHY, the RTL8211B PHY only supports RGMII and MII mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* TSEC driver: Change MDIO support to allow access to any PHYs on the MDIO busmichael.firth@bt.com2008-01-16-20/+12
| | | | | | | | | The current TSEC driver limits MDIO access to the devices that have been configured as attached to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands. Signed-off-by: Michael Firth <michael.firth@bt.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Fix Ethernet init() return codesBen Warren2008-01-10-1/+1
| | | | | | | | | | | | | | | | | | Change return values of init() functions in all Ethernet drivers to conform to the following: >=0: Success <0: Failure All drivers going forward should return 0 on success. Current drivers that return 1 on success were left as-is to minimize changes. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-By: Timur Tabi <timur@freescale.com>
* mpc83xx: Add the support of MPC837xEMDS boardDave Liu2008-01-08-0/+10
| | | | | | | | | | | The MPC837xEMDS board support: * DDR2 400MHz hardcoded and SPD init * Local bus NOR Flash * I2C, UART, MII and RTC * eTSEC RGMII * PCI host Signed-off-by: Dave Liu <daveliu@freescale.com>
* drivers/net : move net drivers to drivers/netJean-Christophe PLAGNIOL-VILLARD2007-11-25-0/+1590
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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