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* phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
* phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
* net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
* net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
* net, phy: fix AR8031 phy_maskHeiko Schocher2013-11-22-1/+1
| | | | | | | | | | | AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944
* net: add function to read/write extended registers in Micrel PhyStefano Babic2013-11-22-0/+32
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* net: fix mask for phy Micrel KSZ9031Stefano Babic2013-11-22-1/+1
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is ↵Bhupesh Sharma2013-11-22-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | detected The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following method to determine which driver is to be loaded for a particular PHY module: list_for_each(entry, &phy_drivers) { drv = list_entry(entry, struct phy_driver, list); if ((drv->uid & drv->mask) == (phy_id & drv->mask)) return drv; } This means that a drv->mask of 0xfffff0 will return incorrect phy driver for the logic above, even if the drv->uid is anything other than something ending with a 0x0. For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then the phy driver selected will always be RTL8211B even though the underlying phy connected on the board is a 8211E module. This patch fixes this issue. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* net: phy/vitesse: Add support for VSC8514 phy moduleArpit Goel2013-11-22-1/+68
| | | | | | | | This patch adds support for VSC8514 PHY module which can be found on Freescale's T1040RDB boards. Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* phylib: update atheros ar803x phyShengzhou Liu2013-11-22-2/+2
| | | | | | | | As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* drivers: net: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-41/+19
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Cosmetic: Fix a number of typos, no functional changes.Robert P. J. Day2013-09-20-1/+1
| | | | | | | Fix various misspellings of things like "environment", "kernel", "default" and "volatile", and throw in a couple grammar fixes. Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* net: phy/realtek: Add support for RTL8211DN and RTL8211E phy modulesBhupesh Sharma2013-08-19-26/+51
| | | | | | | | | | | | This patch adds support for Realtek PHY modules RTL8211DN and RTL8211E (variants: RTL8211E-VB-CG, RTL8211E-VL-CG, RTL8211EG-VB-CG), which can be found on Freescale's T1040RDB boards. To make the driver more generic across 8211 family, a generic name 8211x is added for macros and function names. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* phy: smsc: LAN8710/8720 are not Gbit PHYsFabio Estevam2013-08-19-1/+1
| | | | | | | | LAN8710/8720 are 10/100 Mbps PHYs, so fix the '.features' field. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* net, phy, cpsw: fix gigabit register accessHeiko Schocher2013-07-30-1/+5
| | | | | | | | | | | | | accessing a lan9303 switch with the cpsw driver results in wrong speed detection, as the switch sets the BMSR_ERCAP in BMSR register, and follow read of the MII_STAT1000 register fails, as the switch does not support it. Current code did not check, if a phy_read() fails ... fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-304/+20
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* net: phy: Set SUPPORTED_1000baseX_Half flag in ESTATUS_1000_XHALF caseFabio Estevam2013-07-19-1/+1
| | | | | | | | | | | | | Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the checking for ESTATUS_1000_XHALF, but it incorrectly sets the SUPPORTED_1000baseX_Full flag in this case. Set the SUPPORTED_1000baseX_Half flag instead. Acked-by: Charles Coldwell <coldwell@gmail.com> Reviewed-By: Sascha Silbe <t-uboot@infra-silbe.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* phy: fix 10/100Mbps operation on 1Gbps-capable linksSascha Silbe2013-07-19-1/+9
| | | | | | | | | | | | | | | | | de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a check for the extended status register in order to support 1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since Extended Status only indicates what the PHY (i.e. the local side) is capable of, this broke communication with non-1Gbps peers. Only check the extended status if the 1000BASE-T registers are actually missing so we don't end up setting speed to 1Gbps even though the previous test (for the combination of local and peer support for 1Gbps) already indicated we can't do 1Gbps with the current peer. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* phylib: add atheros ar803x phyHeiko Schocher2013-06-24-1/+12
| | | | | | | | add atheros ar803x phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* phylib: add natsemi dp83630 phyHeiko Schocher2013-06-24-0/+37
| | | | | | | | add natsemi dp83630 phy, used on the upcoming siemens boards. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* net: phy: supplement support for Micrel's KSZ9031SARTRE Leo2013-06-24-1/+35
| | | | | | Add function ksz9031_phy_extended_write and ksz9031_phy_extended_read Signed-off-by: Leo Sartre <lsartre@adeneo-embedded.com>
* phylib: Add Atheros AR8035 GETH PHY supportXie Xiaobo2013-06-24-1/+33
| | | | Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* add support for Xilinx 1000BASE-X phy (GTX)Charles Coldwell2013-06-24-0/+21
| | | | | | | | | | commit 39695029bc15041c809df3db4ba19bd729c447fa Author: Charles Coldwell <coldwell@ll.mit.edu> Date: Tue Feb 19 08:27:33 2013 -0500 Changes to support the Xilinx 1000BASE-X phy (GTX/MGT) Signed-off-by: Charles Coldwell <coldwell@ll.mit.edu>
* PHY: micrel.c: add support for KSZ9031David Andrey2013-06-24-27/+52
| | | | | | | | | | | | Add support for Micrel PHY KSZ9031 in phylib, including small rework for KSZ9021 to avoid code duplication Signed-off-by: David Andrey <david.andrey@netmodule.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Joe Herschberger <joe.hershberger@gmail.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* NET: phy: add 88E1310 PHY initializationSebastian Hesselbarth2013-06-24-0/+48
| | | | | | This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* net: add ICPlus PHY driverYegor Yefremov2013-06-24-0/+98
| | | | | | | The driver code was taken from Linux kernel source: drivers/net/phy/icplus.c Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* phy: export genphy_parse_link()Yegor Yefremov2013-06-24-1/+1
| | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-2/+81
|\ | | | | | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * net/phy: fix select line for TN80xxShaohui Xie2013-05-24-2/+14
| | | | | | | | | | | | | | | | | | | | TN80xx has same PHY ID as TN2020, but it needs different setting to register 30.93 which used to select line, so we read register 30.32 which has bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2, for TN80xx we will get 5 or 4. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * net/phy: add VSC8574 supportShaohui Xie2013-05-14-0/+67
| | | | | | | | | | | | | | | | | | | | The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. This driver supports SGMII and QSGMII MAC mode. For now SGMII mode is tested. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | phy: add support for ET1011C physMatt Porter2013-05-10-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | Adds an ET1011C PHY driver which is derived from the Linux kernel PHY driver (drivers/net/phy/et1011c.c) from the v3.9-rc2 tag. Note that an errata workaround config option is implemented to allow for TX_CLK to be enabled even when gigabit mode is negotiated. This workaround is used on the PG1.0 TI814X EVM. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: phy: Define Marvell 88e1518 phyMichal Simek2013-04-30-0/+11
|/ | | | | | | | This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* phy: add phy_find_by_mask/phy_connect_devTroy Kisky2013-01-28-50/+78
| | | | | | | | | | | | It is useful to be able to try a range of possible phy addresses to connect. Also, an ethernet device is not required to use phy_find_by_mask leading to better separation of mii vs ethernet, as suggested by Andy Fleming. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mv88e61xx: refactor PHY and SWITCH level-codeAlbert ARIBAUD2013-01-09-192/+342
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* phy: Add support for Marvell 88E1118RMichal Simek2012-12-15-0/+11
| | | | | | | | | Marvell 88E1118R has different uid then 88E1118. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Andy Fleming <afleming@freescale.com> CC: Zang Roy-R61911 <tie-fei.zang@freescale.com> CC: Kumar Gala <galak@kernel.crashing.org>
* drivers/net/: sparse fixesKim Phillips2012-11-04-10/+11
| | | | | | | | | | | | | | | | | | | phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static? phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static? phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static? phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static? phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static? phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static? phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static? vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static? tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static? tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static? tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static? eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static? p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static? Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* net/: sparse fixesKim Phillips2012-11-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | bootp.c:44:14: warning: symbol 'dhcp_state' was not declared. Should it be static? bootp.c:45:15: warning: symbol 'dhcp_leasetime' was not declared. Should it be static? bootp.c:46:10: warning: symbol 'NetDHCPServerIP' was not declared. Should it be static? arp.c:30:17: warning: symbol 'NetArpWaitReplyIP' was not declared. Should it be static? arp.c:37:16: warning: symbol 'NetArpTxPacket' was not declared. Should it be static? arp.c:38:17: warning: symbol 'NetArpPacketBuf' was not declared. Should it be static? atheros.c:33:19: warning: symbol 'AR8021_driver' was not declared. Should it be static? net.c:183:7: warning: symbol 'PktBuf' was not declared. Should it be static? net.c:159:21: warning: symbol 'net_state' was not declared. Should it be static? ping.c:73:6: warning: symbol 'ping_start' was not declared. Should it be static? ping.c:82:13: warning: symbol 'ping_receive' was not declared. Should it be static? tftp.c:53:7: warning: symbol 'TftpRRQTimeoutMSecs' was not declared. Should it be static? tftp.c:54:5: warning: symbol 'TftpRRQTimeoutCountMax' was not declared. Should it be static? eth.c:125:19: warning: symbol 'eth_current' was not declared. Should it be static? Note: in the ping.c fix, commit a36b12f95a29647a06b5459198684fc142482020 "net: Move PING out of net.c" mistakenly carried the ifdef CMD_PING clause from when it was necessary to avoid warnings when it was embedded in net.c. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* net: Add Vitesse VSC8662 PHY supportPriyanka Jain2012-09-27-4/+14
| | | | | | | | | | | -VSC8662 is Dual Port 10/100/1000Base-T Phy, 100Base-FX/1000/Base-X Gigabit Ethernt Transceiver Phy. -Its register set and features are similar to other Vitesse Phys Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* net/phy: support the mv88e6352 switchValentin Longchamp2012-09-27-0/+319
| | | | | | | | | | | | | | | | | This patch add support for the configuration of an external switch from the 88E6xxx series from Marvell trough an MDIO link using indirect adressing. This can be used if we do not want to use an EEPROM for the configuration. This driver is not generic and was not tested on other switches than the 88e6352. This is proposed as a first implementation that is somewhat limited but works and that can be used as a basis for further developments for this switch family. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Joe Hershberger <joe.hershberger@gmail.com>
* net: phy: micrel: make ksz9021 phy accessibleTroy Kisky2012-07-11-2/+13
| | | | | | | | | | Micrel accidentally used the same part number for the KS8721 and KSZ9021. So, both cannot be in the same build of u-boot. Add a config option to handle this. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Vladimir Zapolskiy <vz@mleia.com>
* phylib: phy_startup() should return an error code on failureTimur Tabi2012-07-11-1/+4
| | | | | | | phy_startup() calls the PHY driver's startup function, but it ignores the return code from that function, and so it never returns any failures. Signed-off-by: Timur Tabi <timur@freescale.com>
* net: phy: make board_phy_config responsible for calling drv->configTroy Kisky2012-02-27-3/+2
| | | | | | | | | Boards may have things they want done before or after normal phy config. Letting the boards call drv->config allows them more flexibilty. Boards affected by this change are corenet_ds and mpc8544ds. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* net: phy: add support for Micrel's KSZ9021Troy Kisky2012-02-27-0/+87
| | | | | | | | | | | Add the gigabit phy KSZ9021. Also, add function ksz9021_phy_extended_write /_read for access to the phys extended registers. The environment variable "disable_giga" can be used to disable 1000baseTx. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* phy: add Micrel KS8721BL phy definitionVladimir Zapolskiy2011-12-20-0/+11
| | | | | | | | This adds support for the Micrel KS8721BL/SL PHY. The definition is taken from the correspondent datasheet. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* phy: Add support for SMSC LAN87xx PHYsNobuhiro Iwamatsu2011-12-05-0/+96
| | | | | | | | | | | | | | | This adds support for the SMSC LAN87xx PHYs. Following PHYs can be used by set CONFIG_PHY_SMSC to config. - SMSC LAN8700 - SMSC LAN8710/LAN8720 - SMSC LAN8710/LAN8720 A setup of PHY was copied from linux kenrel. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Fixed white space errors; modified commit message a bit. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel codeZang Roy-R619112011-12-05-6/+107
| | | | | | | | | | The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)Timur Tabi2011-10-20-1/+1
| | | | | | | | The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* phylib: wait for TN2020 to achieve SERDES lane alignment at startupTimur Tabi2011-10-13-0/+33
| | | | | | | | | | Before the Teranetics TN2020 PHY can be used, the SERDES lanes need to be aligned, so wait for lane alignment before completing the startup sequence. Note that this process can take up to three seconds. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* phylib: Work around bug in Teranetics PHYAndy Fleming2011-10-09-1/+20
| | | | | | | | | | | The Teranetics PHY does not properly report the link state for fiber connections. The new PHY code actually checked the link, and so the FM driver would refuse to talk over a linkless PHY. But the link may actually be up, so now we always report it as up for fiber connections on the tn2020. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Revert "phylib: remove a couple of redundant code lines"Wolfgang Denk2011-09-28-2/+5
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 041c542219af7f31c372d89b4c7c6f4c8064a8ce. The lines removed by this commit weren't redundant. The logic is (and probably should be better commented): Find the intersection of the advertised capabilities of both sides of the link (lpa). From that intersection, find the highest capability we can run at (that will be the negotiated link). Now imagine that the intersection (lpa) is (LPA_100HALF | LPA_10FULL). The code will now set phydev->speed to 100, and phydev->duplex to 1, but this link does not support 100FULL. Kudos to Andy Fleming <afleming@gmail.com> for binging this to attention and for the explanation. Signed-off-by: Wolfgang Denk <wd@denx.de>
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