summaryrefslogtreecommitdiff
path: root/drivers/net/phy
Commit message (Collapse)AuthorAgeLines
* treewide: replace #include <asm/errno.h> with <linux/errno.h>Masahiro Yamada2016-09-23-1/+1
| | | | | | | | | | | Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have the same content. (both just wrap <asm-generic/errno.h>) Replace all include directives for <asm/errno.h> with <linux/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> [trini: Fixup include/clk.] Signed-off-by: Tom Rini <trini@konsulko.com>
* net: mii: Changes not made by spatchJoe Hershberger2016-08-15-17/+8
| | | | | | | | | | | | | If the functions passed to the registration function are not in the same C file (extern) then spatch will not handle the dependent changes. Make those changes manually. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> For the 4xx related files: Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* net: phy: marvell: Add a missing errno.h headerSimon Glass2016-07-27-0/+1
| | | | | | This corrects a build error on zynqmp. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver: net: phylib: add support for aquantia AQR106/107 PHYMingkai Hu2016-07-06-0/+28
| | | | | | | | This patch adds support for aquantia AQR106/107 PHY. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: marvell: Do not reset 88e1310 after autonegNathan Rossi2016-06-21-4/+1
| | | | | | | | | | | | | | | | | Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
* net: phy: micrel: add support for KSZ886x switches in MIIM modeAlexey Firago2016-06-21-0/+26
| | | | | | | | | | | | | | | | | | | | | | | This patch adds a phy driver for the Micrel KSZ886x switches. Similarly to the KSZ8895, SoC MAC is directly connected to the switch MAC on the switch CPU port, so the link to the switch is always up. KSZ886x switches can be used in the following configuration modes: - Unmanaged mode with config stored in external EEPROM - Managed mode over SPI - Managed mode over I2C - Managed mode over mdio/mdc (aka MIIM or SMI) This patch supports only unmanaged and MIIM modes. Based on Micrel KSZ886x driver from Linux kernel and Micrel KSZ8895 driver from U-Boot. Verified with the KSZ8863MLL. Signed-off-by: Alexey Firago <alexey_firago@mentor.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* nand: Embed mtd_info in struct nand_chipScott Wood2016-06-03-2/+2
| | | | | | | | | | | | nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-05-24-498/+976
|\ | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: drivers/net/zynq_gem.c
| * net: phy: dp83867: Add SGMII helper for configurationDan Murphy2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The code assumed that if the interface is not RGMII configured then it must be SGMII configured. This device has the ability to support most of the MII interfaces. Therefore add the helper for SGMII and only configure the device if the interface is configured for SGMII. Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: Move is_rgmii helper to phy.hDan Murphy2016-05-24-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the phy_interface_is_rgmii to the phy.h file for all phy's to be able to use the API. This now aligns with the Linux kernel based on commit e463d88c36d42211aa72ed76d32fb8bf37820ef1 Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: ti: Allow the driver to be more configurableDan Murphy2016-05-24-10/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the devicetree. If the value is not set in the devicetree then set the delay to the default. If devicetree is not used then use the default defines within the driver. Signed-off-by: Dan Murphy <dmurphy@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: Add PHY driver for mv88e61xx switchesKevin Smith2016-05-24-0/+1020
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous mv88e61xx driver was a driver for configuring the switch, but did not integrate with the PHY/networking system, so it could not be used as a PHY by U-boot. This is a complete rework to support this device as a PHY. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: Remove unused mv88e61xx switch driverKevin Smith2016-05-24-598/+0
| | | | | | | | | | | | | | | | | | | | | | | | No boards are using this driver. Remove in preparation for a new driver with integrated PHY support. Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
* | phy: marvell: Do not reset phy after negotiationMichal Simek2016-05-24-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | phy: Wire return value from phy_config()Michal Simek2016-05-24-3/+1
| | | | | | | | | | | | Fix zynq_gem driver to handle error from phy_config correctly. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | net: phy: Handle phy_startup() error codes properlyMichal Simek2016-05-24-56/+115
| | | | | | | | | | | | | | Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* | phy: Return correct error code when timeout happensMichal Simek2016-05-24-3/+3
|/ | | | | | | Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
* net: phy: Add SGMII support for TI phySiva Durga Prasad Paladugu2016-04-04-1/+38
| | | | | | | | | Add support of SGMII to TI phy dp838367 Enable the SGMII and PCS settings in phy control, CFG2 and BIST registers Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* phy: Add phy driver support for xilinx PCS/PMA coreSiva Durga Prasad Paladugu2016-04-04-0/+148
| | | | | | | | Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: phy: Realtek RTL8211B/C PHY ID fixKarsten Merker2016-04-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047674d7fc9e0aa747273fbc7dcfbac3183 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047674d ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Optionally force master mode for RTL PHYMichael Haas2016-03-31-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this define is set, RTL8211x PHYs (except for the RTL8211F) will have their 1000BASE-T master/slave autonegotiation disabled and forced to master mode. This is helpful for PHYs like the RTL8211C which produce unstable links in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB and A20-OLinuXino-Lime2. There is no proper way to identify affected PHYs in software as the RTL8211C shares its UID with the RTL8211B. Thus, this fix requires the introduction of an #ifdef. CC: fradav@gmail.com CC: merker@debian.org CC: hdegoede@redhat.com CC: ijc@hellion.org.uk CC: joe.hershberger@ni.com Signed-off-by: Michael Haas <haas@computerlinguist.org> Tested-by: Karsten Merker <merker@debian.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* net: phy: atheros: Fix problem with phy_reset() clearing BMCRAlison Wang2016-02-26-0/+3
| | | | | | | | | | | | | | | In commit <a058052c358c> [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION) is cleared too. It causes auto-negotiation timeout error on Atheros's PHY AR8033. To fix this problem, genphy_config_aneg() and genphy_restart_aneg() needs to be called in ar8035_config() to enable and restart auto-negotiation. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Stefan Agner <stefan@agner.ch> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: realtek: Use generic genphy_parse_link() for RTL8211EMichal Simek2016-02-22-1/+9
| | | | | | | | | | | | | | | | | | | | The problem with current implementation is that SPDDONE bit is 1 but link bit is zero. That's why phydev->link is setup to 0 which ending up in driver failure that link is not up. Log: Zynq> dhcp ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done ethernet@e000b000: No link. There is at least 1ms delay between spddone bit and link up. Use genphy_read_status() instead of realtek implemenation which is working with page 11. Linux driver is also using generic implementation. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* net: phy: marvell: Fix problem with phy_reset() clearing BMCRStefan Roese2016-02-18-2/+1
| | | | | | | | | | | | | | | | | | | | | | | With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: marvell: Call phy_reset() where possibleStefan Roese2016-02-18-21/+2
| | | | | | | | | | | | | Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers: net: phy: micrel: fix build errors with CONFIG_DM_ETHMugunthan V N2016-02-08-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Micrel phy is selected without CONFIG_PHY_MICREL_KSZ9031 or CONFIG_PHY_MICREL_KSZ9021 there is a build error. Fixing this by adding proper ifdefs drivers/net/phy/micrel.c:370:39: error: array type has incomplete element type static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = ^ drivers/net/phy/micrel.c:372:39: error: array type has incomplete element type static const struct ksz90x1_reg_field ksz9031_clk_grp[] = ^ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:377:23: error: array type has incomplete element type struct ksz90x1_ofcfg ofcfg[] = { ^ drivers/net/phy/micrel.c:379:13: error: ‘ksz90x1_rxd_grp’ undeclared (first use in this function) { MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 }, ^ drivers/net/phy/micrel.c:379:13: note: each undeclared identifier is reported only once for each function it appears in drivers/net/phy/micrel.c:380:13: error: ‘ksz90x1_txd_grp’ undeclared (first use in this function) { MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 }, ^ drivers/net/phy/micrel.c:386:3: warning: implicit declaration of function ‘ksz90x1_of_config_group’ [-Wimplicit-function-declaration] ret = ksz90x1_of_config_group(phydev, &(ofcfg[i])); ^ drivers/net/phy/micrel.c:377:23: warning: unused variable ‘ofcfg’ [-Wunused-variable] struct ksz90x1_ofcfg ofcfg[] = { ^ drivers/net/phy/micrel.c: At top level: drivers/net/phy/micrel.c:370:39: warning: ‘ksz9031_ctl_grp’ defined but not used [-Wunused-variable] static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = ^ drivers/net/phy/micrel.c:372:39: warning: ‘ksz9031_clk_grp’ defined but not used [-Wunused-variable] static const struct ksz90x1_reg_field ksz9031_clk_grp[] = ^ scripts/Makefile.build:277: recipe for target 'drivers/net/phy/micrel.o' failed make[1]: *** [drivers/net/phy/micrel.o] Error 1 Makefile:1201: recipe for target 'drivers/net/phy' failed make: *** [drivers/net/phy] Error 2 make: *** Waiting for unfinished jobs.... Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers: net: phy: add SMSC LAN8740 Phy support.Purna Chandra Mandal2016-02-01-0/+10
| | | | | | | | | Add SMSC LAN8740 Phy support required for PIC32MZDA devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-38/+96
|\
| * net: phy: implements probe for Cortina phyShaohui Xie2016-01-28-0/+7
| | | | | | | | | | | | | | | | | | Cortina phy cannot support soft reset, this commit implements probe for Cortina PHY to tell phylib to skip phy soft reset by setting PHY_FLAG_BROKEN_RESET in flags. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: introduce a quirk PHY_FLAG_BROKEN_RESETShaohui Xie2016-01-28-0/+3
| | | | | | | | | | | | | | | | | | | | | | Current driver always performs a phy soft reset when connecting the phy device, but soft reset is not always supported by a phy device, so introduce a quirk PHY_FLAG_BROKEN_RESET to let such a phy device to skip soft reset. This commit uses 'flags' of phy device structure to store the quirk. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: micrel: fix divisor value for KSZ9031 phy skewDinh Nguyen2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The picoseconds to register value divisor(ps_to_regval) should be 60 and not 200. Linux has KSZ9031_PS_TO_REG defined to be 60 as well. 60 is the correct divisor because the 4-bit skew values are defined from 0x0000(-420ps) to 0xffff(480ps), increments of 60. For example, a DTS skew value of 420, represents 0ps delay, which should be 0x7. With the previous divisor of 200, it would result in 0x2, which represents a -300ps delay. With this patch, ethernet on the SoCFPGA DE0 Atlas is now able to work with 1Gb ethernet. References: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf -> page 26 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: Use 'autoneg' flag from phydevAlexandre Messier2016-01-28-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the 'autoneg' flag available in phydev when checking if autoneg is in use. The previous implementation was checking directly in the PHY if autoneg was supported. Some PHYs will report that autoneg is supported, even when it is disabled. Thus it is not possible to use that bit to determine if autoneg is currently in use or not. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: Set ANRESTART in setup_forcedAlexandre Messier2016-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When configuring a PHY in fixed (forced) link mode, in order for the changes to be applied, either one of these conditions must be triggered: 1- PHY is reset 2- Autoneg is restarted 3- PHY transitions from power-down to power-up Neither of these is currently done, so effectively the fixed link configuration is not applied in the PHY. Fix this by setting the Autoneg restart bit. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: micrel: Disable B_CAST on configAlexandre Messier2016-01-28-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Micrel PHYs KSZ8021/31 and KSZ8081 have a feature where MDIO address 0 is considered as a broadcast address; the PHY will respond even if it is not its configured (pinstrapped) address. This feature is enabled by default. The Linux kernel disables that feature at initialisation, but not before it probes the MDIO bus. This causes an issue, because a PHY at address 3 will be discovered at addresses 0 and 3, but will then only respond at address 3. Because Linux attaches the first PHY it discovers on 'eth0', it will attach the PHY from address 0, which will never answer again. Fix the issue by disabling the broadcast feature in U-Boot, before Linux is started. Signed-off-by: Alexandre Messier <amessier@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * drivers/net/phy: introduce phy_set_supported()Alexey Brodkin2016-01-28-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | This new function will allow MAC drivers to override supported capabilities of the phy. It is required when MAC cannot handle all speeds supported by phy. For example phy supports up-to 1Gb connections while MAC may only work in modes up to 100 or even 10 Mbit/sec. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: genphy: Allow overwriting featuresSascha Hauer2016-01-28-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_set_phy_supported allows overwiting hardware capabilities of a phy with values from the devicetree. This does not work with the genphy driver though because the genphys config_init function will overwrite all values adjusted by of_set_phy_supported. Fix this by initialising the genphy features in the phy_driver struct and in config_init just limit the features to the ones the hardware can actually support. The resulting features are a subset of the devicetree specified features and the hardware features. This is a copy of the patch from Linux kernel, see http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=c242a47238fa2a6a54af8a16e62b54e6e031d4bc Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: ensure Gigabit features are masked off if requestedFlorian Fainelli2016-01-28-18/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet MAC, the driver will restrict the phydev->supported modes to mask off Gigabit. If the Gigabit PHY comes out of reset with the Gigabit features set by default in MII_CTRL1000, it will keep advertising these feature, so by the time we call genphy_config_advert(), the condition on phydev->supported having the Gigabit features on is false, and we do not update MII_CTRL1000 with updated values, and we keep advertising Gigabit features, eventually configuring the PHY for Gigabit whilst the Ethernet MAC does not support that. This patches fixes the problem by ensuring that the Gigabit feature bits are always cleared in MII_CTRL1000, if the PHY happens to be a Gigabit PHY, and then, if Gigabit features are supported, setting those and updating MII_CTRL1000 accordingly. This is a copy of patch from Linux kernel, see http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=5273e3a5ca94fbeb8e07d31203069220d5e682aa Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * net: phy: do not read configuration register on resetStefan Agner2016-01-28-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | When doing a software reset, the reset flag should be written without other bits set. Writing the current state will lead to restoring the state of the PHY (e.g. Powerdown), which is not what is expected from a software reset. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Michael Welling <mwelling@ieee.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | net: phy: ti: Enable automatic crossover modeMichal Simek2016-01-27-0/+3
| | | | | | | | | | | | | | | | Enable automatic crossover cable detection. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | block: pass block dev not num to read/write/erase()Stephen Warren2016-01-13-1/+2
|/ | | | | | | | | | | This will allow the implementation to make use of data in the block_dev structure beyond the base device number. This will be useful so that eMMC block devices can encompass the HW partition ID rather than treating this out-of-band. Equally, the existence of the priv field is crying out for this patch to exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* phy: atheros: Use ar8035_config for AR8031Fabio Estevam2016-01-07-1/+1
| | | | | | | | | | | | | | | | Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: micrel: Configure KSZ9021/KSZ9031 skew from OFMarek Vasut2015-12-20-1/+145
| | | | | | | | | | | | | | | | Add code to process the KSZ9021/KSZ9031 OF props if they are present and configure skew registers based on the information from the OF. This code is only enabled if the DM support for ethernet is also enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> V2: - Implement struct ksz90x1_reg_field to describe the skew register fields more accurately. - Fix RXDV/TXEN skew register default value and offset.
* net: phy: added aquantia PHY AQR405 supportShaohui Xie2015-11-30-0/+15
| | | | | | | | | The phy can share driver with other aquantia PHYs, so we only add PHY ID. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Move console definitions into a new console.h fileSimon Glass2015-11-19-0/+1
| | | | | | | | The console includes a global variable and several functions that are only used by a small subset of U-Boot files. Before adding more functions, move the definitions into their own header file. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: phy: Add support for Texas Instruments DP83867Edgar E. Iglesias2015-11-19-0/+204
| | | | | | | | | Code is taken from Linux kernel driver (v4.2). Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* pengwyn: nand and ethernet fixesVincent BENOIT2015-11-12-2/+43
| | | | | | -> Add National instrument ethernet transceiver configuration used (DP83848) -> Change cpsw slave phy address -> modify nand configuration to use the correct ECC and correct nand features
* net: phy: Test previous phydev->dev against new mac devBin Meng2015-10-29-1/+1
| | | | | | | | | | In phy_connect_dev(), if the phy device has an accociated mac device before, a warning message will be printed. But we should test the old device against the new one, if they are actually the same one, don't print the warning message. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Change to print all phys that are not foundBin Meng2015-10-29-1/+8
| | | | | | | | | | | In get_phy_device_by_mask(), when no phy is found, currently we only print a message to show the first phy address that is not found. But this is not always the case as multiple phys can be specified by phy_mask. Change to print all phys that are not found, and to reduce the console boot log, change to use 'debug' instead of 'printf'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: Don't create phy device when there is no phyBin Meng2015-10-29-1/+2
| | | | | | | | In get_phy_device_by_mask(), when no phy is found, we should not create any phy device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: micrel: disable NAND-tree for KSZ8051Sylvain Rochet2015-10-29-0/+29
| | | | | | | | | | | | | | | | | | NAND-tree is used to check wiring between MAC and PHY using NAND gates on the PHY side, hence the name. NAND-tree initial status is latched at reset by probing the IRQ pin. However some devices are sharing the PHY IRQ pin with other peripherals such as Atmel SAMA5D[34]x-EK boards when using the optional TM7000 display module, therefore they are switching the PHY in NAND-tree test mode depending on the current IRQ line status at reset. This patch ensure PHY is not in NAND-tree test mode only for the Micrel KSZ8051 PHY used by Atmel. There are other Micrel PHY affected but I doubt they are used on such weird hardware design. Signed-off-by: Sylvain Rochet <sylvain.rochet@finsecur.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
generated by cgit v1.1 at 2024-11-08 13:54:46 +0000