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* net: phy: micrel: add support for KSZ8021RNL & KSZ8031RNLSylvain Lemieux2015-10-29-0/+11
| | | | | | | This patch adds support for Micrel KSZ8021RNL & KSZ8031RNL. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: on phy device create do not initialize link to 1Mugunthan V N2015-09-29-1/+1
| | | | | | | | | | | | | | | | Currently when phy device is created the link variable is initialized to 1 which denoted phy link is already up. On a power reset there is no issue as phy status register link status will not be set, so phy auto negotiate will be started. But when a cpu reset is issued (ex: dra72x-evm) phy's link status bit is already set which leads to assume that link is already setup in genphy_update_link() initial check which results in ehternet not working. So do not assume that link is already up and on phy device create set link to zero. This is verified on dra72x-evm. Reported-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy/vitesse: Add support for VSC8584 phyPrabhakar Kushwaha2015-09-01-0/+11
| | | | | | | | | | Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: phy: broadcom: Add BCM Cygnus PHYJiandong Zheng2015-08-11-0/+29
| | | | | | | | Add Ethernet PHY for BCM Cygnus SoC Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: delay only if reset handler is registeredJörg Krause2015-08-11-3/+5
| | | | | | | | With commit e3a77218a256edbe201112a39beeed8adcabae3f the MII bus is only reset if a reset handler is registered. If there is no reset handler there is no need to wait for a device to come out of the reset. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* net: phy: fix data type of phy_idJörg Krause2015-08-11-1/+1
| | | | | | phy_id is declared as u32 in create_phy_by_mask and in struct phy_device. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* net: Add support for Marvell 88E1510 PHYClemens Gruber2015-08-11-0/+30
| | | | | | | | | | | Support the 88E1510 PHY which is very similar to the 88E1518. I also set the INTn output and configured the LEDs. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: Improve 88E151x PHY initializationClemens Gruber2015-08-11-14/+23
| | | | | | | | | | | - The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy: set led for rtl8211f phyShengzhou Liu2015-08-11-0/+8
| | | | | | | Initialize LCR rigister to configure green LED for Link, yellow LED for Active. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* net: phy: Add support for all targets which requires MANUAL_RELOCMichal Simek2015-05-19-0/+16
| | | | | | | | | | | Targets with CONFIG_NEEDS_MANUAL_RELOC do not use REL/RELA relocation (mostly only GOT) where functions aray are not updated. This patch is fixing function pointers passed to phy_register function. This patch was tested on Microblaze architecture. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy: refactor RTL8211F initializationShengzhou Liu2015-05-19-8/+25
| | | | | | | | | | RTL8211F needs to enalbe TXDLY for RGMII during phy initialization, so move it to rtl8211f_config for early initialization. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy: Add support for realtek RTL8211FShengzhou Liu2015-05-19-0/+85
| | | | | | | | | RTL8211F has different registers from RTL8211E. This patch adds support for RTL8211F PHY which can be found on Freescale's T1023 RDB board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net/phy/cortina: Fix compilation warningpankaj chauhan2015-04-23-2/+2
| | | | | | | | Fix comilation warning which is emitted when firmware address is more than 32 bit. Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* net/phy: fixup for get_phy_idShengzhou Liu2015-04-20-1/+1
| | | | | | | | commit 3c6928fd7b0f84 "net: phy: fix warnings with W=1" caused some PHYs(e.g. CS4315/CS4340) not working. This patch fixes the warning and make those special PHYs working as well. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* net: phy: micrel: add support for KSZ8081MNXLuca Ellero2015-04-20-0/+11
| | | | | | | This patch adds a support for KSZ8081MNX in MII mode. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com> Acked-by: Pavel Machek <pavel@denx.de>
* net: phy: realtek: Disable interrupt on Realtek Ethernet PHY driversCodrin Ciubotariu2015-04-20-1/+17
| | | | | | | | | | | | | | | Some Realtek Ethernet PHYs, like RTL8211D(G/N) and RTL8211E(G), have interrupts enabled by default. If the interrupt is not treated later by the OS and the PHY's interrupt line is enabled and shared with other interrupts, the system will get an interrupt storm. This patch disables the interrupt for PHY devices that use one of the current Realtek Ethernet PHY drivers. Some of Realtek Ethernet PHYs, such as RTL8211B(L) have the interrupt masked. In this case, the functionality of the PHY should not be afected since this patch brings INER and INSR registers to their default values. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: net: Adjust PHY interface to work with CONFIG_DM_ETHSimon Glass2015-04-18-0/+22
| | | | | | | | | | | | When driver model is used for Ethernet a few functions are passed a udevice instead of an eth_device. Also add a function to find a PHY type given its name. This will be used to decode the device tree node. Finally, put a phy_interface field in struct eth_pdata since this is an important part of the platform data for Ethernet. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* net: phy: micrel: add support for KSZ8895 switch in SMI modePhilippe De Muyter2015-01-30-0/+58
| | | | | | | | | | | | | | | | | | | This patch adds a phy driver for the Micrel KSZ8895 switch. As the SoC MAC is directly connected to the switch MAC the link to the switch is always up. But the KSZ8895 switch can be hardwired in three configuration modes : - not configurable with eventually an eeprom-stored configuration - configurable by the mdio/mdc connection (SMI protocol) - configurable by a SPI connection. In not configurable mode, the switch starts automatically, but in the other modes, it must be started programmatically, by writing 1 in configuration register 1. We only support the not configurable and mdio/mdc (aka SMI) modes here. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* phylib: add support for aquantia PHYsShaohui Xie2015-01-16-0/+160
| | | | | | | | This patch supports AQ1202, AQ2104, AQR105 PHY. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/phy: enable serdes auto-negotiation for vsc8514 phyShengzhou Liu2014-12-05-2/+11
| | | | | | | | VSC8514 QSGMII PHY requires enabling auto-negotiation, otherwise it wouldn't work. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/phy: Add support for CS4315/CS4340 PHYShengzhou Liu2014-12-05-0/+337
| | | | | | | | | | | | Add support for Cortina CS4315/CS4340 10G PHY. - This driver loads CS43xx firmware from NOR/NAND/SPI/SD device to initialize Cortina PHY. - Cortina PHY has non-standard offset of PHY ID registers, thus we define own get_phy_id() to override default get_phy_id(). - To define macro CONFIG_PHY_CORTINA will enable this driver. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: phy: marvell: add errata w/a for 88E151* chipsHao Zhang2014-11-06-1/+52
| | | | | | | | | | | As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-10-27-1/+1
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| * net: phy: print a number of phy that is not foundKhoronzhuk, Ivan2014-10-23-1/+1
| | | | | | | | | | | | | | | | In case when several Ethernet ports are supported it's convenient to see the number of phy that is not found. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | net: phy: fix warnings with W=1Jeroen Hofstee2014-10-25-5/+2
|/ | | | | | | | get_phy_id is marked weak but has no protype nor a strong version, just make it static. Use __weak for board_phy_config. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* net: phy: Cleanup drivers/net/phy/micrel.cPavel Machek2014-10-06-4/+3
| | | | | | | | | | | | | | | | Old saying says that more than three exclamation marks in a row are sign of mental disease. Cleanup micrel.c. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Chin Liang See <clsee@altera.com>
* drivers: net: remove dead driversMasahiro Yamada2014-08-21-84/+0
| | | | | | | | | | The following configs are not defined at all: - CONFIG_INCA_IP_SWITCH - CONFIG_PBL2800_ETHER - CONFIG_PHY_ICPLUS Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* vitesse: remove duplicated argument to ||maxin.john@enea.com2014-08-09-1/+0
| | | | | | Remove the duplicated argument to || check Signed-off-by: Maxin B. John <maxin.john@enea.com>
* phy: fix create_phy_by_mask for when its given an actual search maskCormier, Jonathan2014-06-05-3/+1
| | | | | | | | | | | | | | | | get_phy_id returns -EIO when it can't read from a phy at a given addr. This would cause create_phy_by_mask to return prematurely before it had tested the other addresses in the provided mask. Example usage: Replace phydev = phy_connect(bus, phy_addr, dev, phy_if) with phydev = phy_find_by_mask(bus, phy_mask, phy_if) if (phydev) phy_connect_dev(phydev, dev); Signed-off-by: Cormier, Jonathan <jcormier@criticallink.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* net: phy/vitesse: Add support for VSC8664 phy moduleChunhe Lan2014-05-16-0/+46
| | | | | | | | This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/phy: enable get_phy_id redefinableShengzhou Liu2014-05-12-1/+2
| | | | | | | | | As some PHYs have non-standard PHY ID registers, PHY Id can't be read correctly by current get_phy_id function, so we enable get_phy_id redefinable to permit specific PHY driver having own specific get_phy_id function. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* AR8035/phy: Enable autonegotiation function for ar8035Xiaobo Xie2014-05-12-3/+1
| | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
* ar8031: modify the config func of ar8031 to ar8021_configZhao Qiang2014-04-22-1/+1
| | | | | | | | ar8031 has the same config steps with ar8021, so change its config func to ar8021_config instead of genphy_config. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/phy: Fix PHY id for VSC8514Codrin Ciubotariu2014-04-22-1/+1
| | | | | | | | | | In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/phy: Correct AR8021 phy_maskHaijun.Zhang2014-03-07-1/+1
| | | | | | | | There was wrong phy_mask for AR8021 device, so the AR8021 can't be probed correctly. Changed it from 0x4fffff to 0x4ffff0. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-02-25-0/+1
|\ | | | | | | | | | | | | With this, fixup a trivial build error of get_effective_memsize needing to be updated in the new board/freescale/p1010rdb/spl.c Signed-off-by: Tom Rini <trini@ti.com>
| * ar8031/8033/phy:enable autonegotiation for ar8031/8033Zhao Qiang2014-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | net, phy: atheros ar803x bugHeiko Schocher2014-02-19-1/+1
|/ | | | | | | | | | | | | | commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* net: phy: atheros: Fix the masks for AR8031/8035Fabio Estevam2014-01-14-2/+2
| | | | | | | | | | | | | Use the same masks as used in the kernel: https://git.kernel.org/cgit/linux/kernel/git/stable/linux-stable.git/tree/drivers/net/phy/at803x.c?id=refs/tags/v3.12.6 With such changes Ethernet is functional on hummingboard solo. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Marek Vasut <marex@denx.de> Patch: 306640
* phy: Use general phy code for smsc lan8720aDavid Dueck2013-11-22-1/+2
| | | | Signed-off-by: David Dueck <davidcdueck@googlemail.com>
* phy: Use supported field during autonegotiationDavid Dueck2013-11-22-2/+3
| | | | | | | The current code incorrectly detects gigabit capabilities for some 100Mbit/s phys. (lan8720a) Signed-off-by: David Dueck <davidcdueck@googlemail.com>
* net: phy: atheros: Fix masks for AR8035 and AR8021Fabio Estevam2013-11-22-1/+1
| | | | | | | | | The masks were ignoring the last 4 bits which didn't allow detection differences between the ar8031 and ar8035. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Patch: 288018
* net/phy: Fix the phy id mask of AR8031Chunhe Lan2013-11-22-1/+1
| | | | | | | | | | | | The both AR8031 and AR8035 belong to Atheros 803x serial PHY. So the phy id mask of AR8031 is the same to the phy id mask of AR8035. The right mask value is 0x4fffff. This patch has been tested on the P1010 and P1023. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 287748
* net, phy: fix AR8031 phy_maskHeiko Schocher2013-11-22-1/+1
| | | | | | | | | | | AR8035 driver will be never applied because of wrong mask for AR8031 driver. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Pavel Nakonechny <pavel.nakonechny@skitlab.ru> Cc: Andy Fleming <afleming@freescale.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Patch: 276944
* net: add function to read/write extended registers in Micrel PhyStefano Babic2013-11-22-0/+32
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* net: fix mask for phy Micrel KSZ9031Stefano Babic2013-11-22-1/+1
| | | | Signed-off-by: Stefano Babic <sbabic@denx.de>
* net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is ↵Bhupesh Sharma2013-11-22-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | detected The 'get_phy_driver' code in 'drivers/net/phy/phy.c' uses the following method to determine which driver is to be loaded for a particular PHY module: list_for_each(entry, &phy_drivers) { drv = list_entry(entry, struct phy_driver, list); if ((drv->uid & drv->mask) == (phy_id & drv->mask)) return drv; } This means that a drv->mask of 0xfffff0 will return incorrect phy driver for the logic above, even if the drv->uid is anything other than something ending with a 0x0. For e.g. if the RTL8211E drv->uid is 0x1cc915 and drv->mask is 0xffffff and the RTL8211B drv->uid is 0x1cc910 and drv->mask is 0xffffff0, then the phy driver selected will always be RTL8211B even though the underlying phy connected on the board is a 8211E module. This patch fixes this issue. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* net: phy/vitesse: Add support for VSC8514 phy moduleArpit Goel2013-11-22-1/+68
| | | | | | | | This patch adds support for VSC8514 PHY module which can be found on Freescale's T1040RDB boards. Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
* phylib: update atheros ar803x phyShengzhou Liu2013-11-22-2/+2
| | | | | | | | As AR8031 and AR8033 have same PHY ID 0x4dd074, they use the common driver. Currently AR8031_driver didn't work for AR8033, hence updated it to have it work on AR8031/AR8033. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* drivers: net: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-41/+19
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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