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path: root/drivers/net/pcnet.c
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* pcnet: force ordering of descriptor accessesPaul Burton2014-04-18-18/+19
| | | | | | | | | | | The ordering of accesses to the rx & tx descriptors is important, yet the send & recv functions accessed them via regular structure accesses. This leaves the compiler with the opportunity to reorder those accesses or to hoist them outside of loops. Prevent that from happening by using readl & writel to access the descriptors. As a nice bonus, this removes the need for the driver to care about endianness. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: align rx buffers for cache invalidationPaul Burton2014-04-18-9/+12
| | | | | | | | | | The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: access descriptor rings & init block uncachedPaul Burton2014-04-18-31/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | The prior accesses to the descriptor rings & init block via cached memory had a few issues: - The memory needs cache flushes or invalidation at the appropriate times, but was not necessarily aligned on cache line boundaries. This could lead to data being incorrectly lost or written back to RAM at the wrong time. - There are points where ordering of writes to the memory is important, but because it's cached memory the pcnet controller would see cache lines written back ordered by address. This could occasionally lead to hardware seeing descriptors in an incorrect state. - Flushing the cache constantly is inefficient. So, to avoid all of those issues simply access the descriptors & init block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is used to do this (retrieving an address in kseg1) as I could see no existing generic solution. Since the MIPS Malta board is the only user of the pcnet driver, hopefully this doesn't matter. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* MPC824x: remove obsolete "PN62" boardWolfgang Denk2013-11-11-10/+0
| | | | | | | | | | | The MPC824x processors have long reached EOL, and the PN62 board has not seen any board-specific updates for more than a decade. It is now causing build issues. Instead of wasting time on things nobody is interested in any more, we rather drop this board. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@grandegger.com> cc: Tom Rini <trini@ti.com>
* pcnet: enable the NOUFLO featurePaul Burton2013-11-09-0/+15
| | | | | | | | | | | | | | On relatively slow boards (such as the MIPS Malta with an FPGA core card) it can be extremely common for transmits to underflow - to the point where it appears they simply do not work at all. Setting the NOUFLO bit causes the ethernet controller to not begin transmission on the wire until a transmit start point is reached. Setting that transmit start point to the full packet will cause the controller to only transmit the packet once it has buffered it entirely thus preventing any transmit underflows from occuring and allowing the controller to function on slower boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: add cache flushing & invalidationPaul Burton2013-11-09-0/+16
| | | | | | | | | | | Ensure that the view of memory from the CPU & the ethernet controller is coherent at the various points where they exchange data. This prevents stale data from being transmitted or received, and prevents the driver from getting stuck waiting for the ethernet controller to update descriptors when in reality it has but the old values are being read from cache. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: s/le16_to_cpu/cpu_to_le16/ in pcnet_sendPaul Burton2013-11-09-2/+2
| | | | | | | This should cause no change to the generated code, but is semantically correct. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* pcnet: code style cleanupPaul Burton2013-11-09-125/+123
| | | | | | | | | Fix up the code to match Documentation/CodingStyle. This is mostly removing extraneous spaces. No functional change is intended. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* net: pcnet: use pci_virt_to_mem to obtain buffer addressesGabor Juhos2013-07-24-1/+1
| | | | | | | | | | | | | | The pcnet driver uses the pci_phys_to_mem function to get the memory address of the DMA buffers. This This assumes an 1:1 mapping between the PCI and physical memory which is not true on all platforms. On MIPS platform U-Boot is running within a mapped memory region, and the pci_phys_to_mem macro can't be used to obtain the memory address of the buffers. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* drivers/net/pcnet.c: Fix compile warningJoe Hershberger2012-05-22-4/+2
| | | | | | | | Fix this: pcnet.c: In function 'pcnet_initialize': pcnet.c:224:13: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* drivers/net/pcnet.c: Change debug code to fix build warningWolfgang Denk2011-11-07-13/+4
| | | | | | | | | | Fix: pcnet.c: In function 'pcnet_probe': pcnet.c:247:8: warning: variable 'chipname' set but not used [-Wunused-but-set-variable] Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Wolfgang Grandegger <wg@denx.de>
* net: pcnet: Add initialized eth_device structureNobuhiro Iwamatsu2010-11-14-0/+5
| | | | | | | | | pcnet driver does not have write_hwaddr function. However, eth stuff executes write_hwaddr function because eth_device structure has not been initialized. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of PCNET Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+1
| | | | | | | | | | Affected boards: PN62 sc520_cdp Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* net: Conditional COBJS inclusion of network driversShinya Kuribayashi2008-06-09-4/+0
| | | | | | | Replace COBJS-y with appropriate driver config names. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* pcnet.c: fix a merge issueWolfgang Denk2008-04-28-54/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fixed pcnet io_baseVlad Lungu2008-04-24-0/+55
| | | | | | Bus and phys address are not always the same Signed-off-by: Vlad Lungu <vlad@comsys.ro>
* drivers/net/pcnet.c: Coding Style cleanup.Wolfgang Denk2008-04-24-360/+370
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Added Am79C970A chip id to pcnetVlad Lungu2008-04-24-0/+3
| | | | Signed-off-by: Vlad Lungu <vlad@comsys.ro>
* Fix Ethernet init() return codesBen Warren2008-01-10-2/+2
| | | | | | | | | | | | | | | | | | Change return values of init() functions in all Ethernet drivers to conform to the following: >=0: Success <0: Failure All drivers going forward should return 0 on success. Current drivers that return 1 on success were left as-is to minimize changes. Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Acked-By: Timur Tabi <timur@freescale.com>
* drivers/net : move net drivers to drivers/netJean-Christophe PLAGNIOL-VILLARD2007-11-25-0/+526
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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