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path: root/drivers/net/fm
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* Freescale t104x: Do not exclude SGMIIJoakim Tjernlund2014-12-05-4/+0
| | | | | | | | | | | | fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE. This excludes testing for SGMII further down. Remove the unconditional "else return PHY_INTERFACE_MODE_NONE" so SGMII can be tested too. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: add 2.5G SGMII supportShengzhou Liu2014-11-19-4/+12
| | | | | | | | | | As auto-negotiation is not supported for 2.5G SGMII, we need to add a new type PHY_INTERFACE_MODE_SGMII_2500 to differentiate SGMII-1G and SGMII-2.5G with different setting for auto-negotiation. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/net/fm/memac_phy: set NEG bit for external MDIOsShaohui Xie2014-11-14-1/+4
| | | | | | | | | | NEG bit default is '1' for external MDIOs as per FMAN-v3 RM, but on some platforms, e.g. T2080QDS, this bit is '0', which leads to MDIO failure on XAUI PHY, so set this bit definitely to align with the RM. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Fman/mEMAC: mEMAC fix for 10G MAC and PHYShaohui Xie2014-11-14-3/+11
| | | | | | | | | | | | 1. use Payload length check disable when enable MAC; 2. add XGMII support for setting MAC interface mode; 3. only enable auto negotiation for Non-XGMII mode; 4. return 0xffff if clause 22 is used to read 10G phy_id; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-By: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-24-2/+0
| | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
* net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil2014-09-08-4/+2
| | | | | | | | | | | | | | | fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* powerpc/T4240QDS/eth: some fix for XFIShaohui Xie2014-08-20-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XFI is supported on T4QDS-XFI board, which removed slot3, and four LANEs of serdes2 are routed to a SFP+ cages, which to house fiber cable or direct attach cable(copper), the copper cable is used to emulate the 10GBASE-KR scenario. So, for XFI usage, there are two scenarios, one will use fiber cable, another will use copper cable. For fiber cable, there is NO PHY, while for copper cable, we need to use internal PHY which exist in Serdes to do auto-negotiation and link training, which implemented in kernel. We use hwconfig to define cable type for XFI, and fixup dtb based on the cable type. For copper cable, set below env in hwconfig: fsl_10gkr_copper:<10g_mac_name> the <10g_mac_name> can be fm1_10g1, fm1_10g2, fm2_10g1, fm2_10g2. The four <10g_mac_name>s do not have to be coexist in hwconfig. For XFI ports, if a given 10G port will use the copper cable for 10GBASE-KR, set the <10g_mac_name> of the port in hwconfig, otherwise, fiber cable will be assumed to be used for the port. For ex. if four XFI ports will both use copper cable, the hwconfig should contain: fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm2_10g1,fm2_10g2 For fiber cable: 1. give PHY address to a XFI port, otherwise, the XFI ports will not be available in U-boot, there is no PHY physically for XFI when using fiber cable, this is just to make U-boot happy and we can use the XFI ports in U-boot. 2. fixup dtb to use fixed-link in case of fiber cable which has no PHY. Kernel requests that a MAC must have a PHY or fixed-link. When using XFI protocol, the MAC 9/10 on FM1 should init as 10G interface. Change serdes 2 protocol 56 to 55 which has same feature as 56 since 56 is not valid any longer. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Change Andy Fleming's email addressAndy Fleming2014-08-06-2/+2
| | | | | | | Messages to afleming@freescale.com now bounce, and should be directed to my personal address at afleming@gmail.com Signed-off-by: Andy Fleming <afleming@gmail.com>
* net/fm: call fm_port_to_index() with proper checksRotariu Marian-Cristian2014-07-22-1/+8
| | | | | | | | Some of the fm_port_to_index() callers did not check for -1 return value and used -1 as an array index. Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/85xx: add T4080 SoC supportShengzhou Liu2014-05-13-0/+1
| | | | | | | | The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/fman/memac: use default MDIO_HOLD valueShaohui Xie2014-05-13-6/+2
| | | | | | | | Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* driver/net/fm/memac_phy: Initialize mdio_clock for SoCs wih FMANv3Priyanka Jain2014-04-22-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MDIO clock needs to be initialized in u-boot code for SoCs having FMAN-v3(v3H or v3L) controller due to below reasons -On SoCs that have FMAN-v3H like B4860, default value of MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates mdio clock too high (much higher than 2.5MHz), violating the IEEE specs. -On SOCs that have FMAN-v3L like T1040, default value of MDIO_CLK_DIV bits is zero, so MDIO clock is disabled. So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to be properly initialized. Also this type of initialization is generally done in PBI(pre-bootloader) phase using rcw.But for chips like T1040 which support deep-sleep, such type of initialization cannot be done in PBI phase due to the limitation that during deep-sleep resume, FMAN (MDIO) registers are not accessible in PBI phase. So, mdio clock initailization must be done as part of u-boot. This initialization code is implemented in memac_phy.c which gets compiled only for SoCs having FMANv3, so no extra compilation flag is required. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-22-6/+6
| | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* boards/t1040qds: Adds ethernet support for T1040Prabhakar Kushwaha2014-02-03-0/+56
| | | | | | | | | | | | | | | | | Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
* net/fm: revert commit 732dfe090d50af53bb682d0c8971784f8de1f90fShengzhou Liu2014-01-21-52/+1
| | | | | | | | This patch reverts patch 'add ft_fixup_xgec to support 3rd and 4th 10GEC'. When dual-role MAC acts as 10G,it still uses fsl,fman-port-1g-rx/tx as before. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/t2080qds: some update for t2080qdsShengzhou Liu2014-01-21-4/+6
| | | | | | | | | | - add more serdes protocols support. - fix some serdes lanes route. - fix SGMII doesn't work and incorrect mdio display for XFI when serdes 0x6d. - correct boot location info for SD/SPI boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fman: add ft_fixup_xgec to support 3rd and 4th 10GECShengzhou Liu2013-12-11-1/+52
| | | | | | | | | As mEMAC1 and mEMAC2 are dual-role MACs, which are used as 1G or 10G MAC. So we update dynamically 'cell-index' to '2' and '3' for 10GEC3 and 10GEC4. Also change 'fsl,fman-port-1g-rx' to 'fsl,fman-port-10g-rx', ditto for Tx. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Add T2080/T2081 SoC supportShengzhou Liu2013-11-25-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* net/fman: Add support for 10GEC3 and 10GEC4Shengzhou Liu2013-11-25-6/+26
| | | | | | | There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* drivers/net/fm: descend only when CONFIG_FMAN_ENET=yMasahiro Yamada2013-11-17-2/+0
| | | | | | | CONFIG_FMAN_ENET is defined only for CPU mpc85xx. We do not need to filter by CPU mpc85xx. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/t1040: Update defines to support T1040SoC personalitiesPriyanka Jain2013-11-13-0/+3
| | | | | | | | | | | | | | | | T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com>
* drivers: net: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-41/+20
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* net/fman: add a fm_enable_port functionValentin Longchamp2013-10-24-0/+51
| | | | | | | | | | This can be useful if one wants to disable an interface in u-boot because u-boot should not manage it but then later reenable it for FDT fixing or if the kernel uses this interface. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix conflict in fm_eth.h] Acked-by: York Sun <yorksun@freescale.com>
* powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-16-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang2013-10-16-0/+45
| | | | | | | | | | | | | | | | | | | | | Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
* powerpc/t4240: add QSGMII interface supportShaohui Xie2013-08-20-2/+43
| | | | | | | | | | Also some fix for QSGMII. 1. fix QSGMII configure of Serdes2. 2. fix PHY address of QSGMII MAC9 & MAC10 for each FMAN. 3. fix dtb for QSGMII interface. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* drivers/fm: Fix compiling error if FW location is not definedYork Sun2013-08-09-0/+2
| | | | | | | FMAN firmware can be in NOR flash, NAND flash, SPI flash, MMC or even remote. In case none of them is defined, set it to null. Signed-off-by: York Sun <yorksun@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-227/+16
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Enable XAUI interface for B4860QDSSuresh Gupta2013-05-24-2/+4
| | | | | | | | | | | | | - Added SERDES2 PRTCLs = 0x98, 0x9E - Default Phy Addresses for Teranetics PHY on XAUI card The PHY addresses of Teranetics PHY on XAUI riser card are assigned based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1 and slot2 - Configure MDIO for 10Gig Mac Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* net/fm: fixup ethernet for mEMACShengzhou Liu2013-05-14-0/+27
| | | | | | | | | - set proper compatible property name for mEMAC. - fixed ft_fixup_port for dual-role mEMAC, which will lead to MAC node disabled incorrectly. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add T4160 SoCYork Sun2013-05-14-0/+1
| | | | | | | | | | T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fman/t4240: some fix for 10G XAUIShaohui Xie2013-05-14-4/+18
| | | | | | | | | | 1. fix 10G mac offset by plus 8; 2. add second 10G port info for FM1 & FM2 when init ethernet info; 3. fix 10G lanes name to match lane protocol table; Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+17
| | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* net: Use new numeric setenv functionsSimon Glass2013-02-28-3/+1
| | | | | | Use setenv_ulong(), setenv_hex() and setenv_addr() in net/ Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx:Add support of B4420 SoCPoonam Aggrwal2013-01-30-0/+1
| | | | | | | | | | | | | | | | | | | | | B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Few updates for B4860 cpu changesPoonam Aggrwal2013-01-30-0/+79
| | | | | | | | | | | | | | | - Added some more serdes1 and serdes2 combinations serdes1= 0x2c, 0x2d, 0x2e serdes2= 0x7a, 0x8d, 0x98 - Updated Number of DDR controllers to 2. - Added FMAN file for B4860, drivers/net/fm/b4860.c Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-0/+114
| | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* drivers/net/: sparse fixesKim Phillips2012-11-04-9/+9
| | | | | | | | | | | | | | | | | | | phy.c:46:5: warning: symbol 'genphy_config_advert' was not declared. Should it be static? phy.c:121:5: warning: symbol 'genphy_setup_forced' was not declared. Should it be static? phy.c:468:5: warning: symbol 'phy_probe' was not declared. Should it be static? phy.c:491:19: warning: symbol 'get_phy_driver' was not declared. Should it be static? phy.c:508:19: warning: symbol 'phy_device_create' was not declared. Should it be static? phy.c:552:5: warning: symbol 'get_phy_id' was not declared. Should it be static? phy.c:584:19: warning: symbol 'get_phy_device' was not declared. Should it be sta vitesse.c:126:5: warning: symbol 'vsc8601_config' was not declared. Should it be static? vsc7385.c:33:5: warning: symbol 'vsc7385_upload_firmware' was not declared. Should it be static? tgec_phy.c:33:5: warning: symbol 'tgec_mdio_write' was not declared. Should it be static? tgec_phy.c:75:5: warning: symbol 'tgec_mdio_read' was not declared. Should it be static? tgec_phy.c:117:5: warning: symbol 'tgec_mdio_reset' was not declared. Should it be static? eth.c:48:6: warning: symbol 'dtsec_configure_serdes' was not declared. Should it be static? p4080.c:26:5: warning: symbol 'port_to_devdisr' was not declared. Should it be static? Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* powerpc/fm: fix TBI PHY address settingsshaohui xie2012-10-22-2/+2
| | | | | | | | | | | | | | | | TBI PHY address (TBIPA) register is set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c, and it is supposed to set TBIPA on FM1@DTSEC1 in case of FM1@DTSEC1 isn't used directly, which provides MDIO for other ports. So following code is wrong in case of FM2, which has a different mac base. struct dtsec *regs = (struct dtsec *)fm_eth->mac->base; /* Assign a Physical address to the TBI */ out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE); Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fm/mEMAC: add mEMAC frame workRoy Zang2012-10-22-2/+323
| | | | | | | | | | | The multirate ethernet media access controller (mEMAC) interfaces to 10Gbps and below Ethernet/IEEE 802.3 networks via either RGMII/RMII interfaces or XAUI/XFI/SGMII/QSGMII using the high-speed SerDes interface. Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add B4860 and variant SoCsYork Sun2012-10-22-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: Add T4240 SoCYork Sun2012-10-22-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-23-1/+0
| | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-98/+0
| | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fm-eth: use fdt_status_disabled() function in ft_fixup_port()Timur Tabi2012-08-23-6/+5
| | | | | | | | We have a dedicated function for setting the node status now, so use it. Also improve a comment and fix the type of the phandle variable. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* fm-eth: add function fm_info_get_phy_address()Timur Tabi2012-08-23-0/+16
| | | | | | | | | Function fm_info_get_phy_address() returns the PHY address for a given Fman port. This is handy when the MDIO code needs to fixup the Ethernet nodes in the device tree to point to PHY nodes for a specific PHY address. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: add support for FM2 DTSEC5Timur Tabi2012-08-23-0/+3
| | | | | | | | Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* net: abort network initialization if the PHY driver failsTimur Tabi2012-07-11-1/+8
| | | | | | | | | | Now that phy_startup() can return an actual error code, check for that error code and abort network initialization if the PHY fails. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part) Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac) Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
* drivers/net/fm/eth.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | Fix this: eth.c: In function 'fm_eth_initialize': eth.c:651:12: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* powerpc/corenet_ds: Slave module for boot from SRIOLiu Gang2012-04-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
generated by cgit v1.1 at 2024-12-24 16:30:08 +0000