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path: root/drivers/net/fec_mxc.c
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* net: fec_mxc: make local functions staticJeroen Hofstee2014-10-25-3/+5
| | | | Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-09-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-09-2/+10
| | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* NET: fec_mxc: fix MDIO clock prescaler calculationMarkus Niebel2014-02-11-2/+6
| | | | | | | | | | The prescaler value for MDC is calculated wrong for MX6S. Implement the same logic as linux here which handles ENET_MAC different then original FEC. Tested on a custom board with i.MX6S and 100MBit PHY Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
* Net: FEC: Fix huge memory leakMarek Vasut2013-11-21-78/+99
| | | | | | | | | | | The fec_halt() never free'd both RX and TX DMA descriptors that were allocated in fec_init(), nor did it free the RX buffers. Rework the FEC driver so that these descriptors and buffers are allocated only once in fec_probe(). Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* net: fec_mxc: Fix timeouts during tftp transferFabio Estevam2013-09-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | Performing tftp transfers on mx28 results in random timeouts. Hector Palacios and Robert Hodaszi analyzed the root cause being related to the wrong alignment of the 'buff' buffer inside fec_recv(). Benoît Thébaudeau provided an excellent analysis of the alignment bug that is present on older versions, such as GCC 4.5.4: http://marc.info/?l=u-boot&m=137942904906131&w=2 Use ALLOC_CACHE_ALIGN_BUFFER() to avoid alignment issues from older GCC versions. Reported-by: Hector Palacios <hector.palacios@digi.com> Tested-by: Oliver Metz <oliver@freetz.org> Tested-by: Hector Palacios <hector.palacios@digi.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* net: fec_mxc: Add support for mx6 solo-liteFabio Estevam2013-09-20-1/+1
| | | | | | | | | Similarly as mx25 and mx53, mx6solo-lite needs to setup the MII gasket for RMII mode. Add support for mx6solo-lite. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* fec_mxc: set ethaddr if fuses burned and not previously setEric Nelson2013-08-21-0/+2
| | | | | | | | | Without this change, the following message is generated: Warning: FEC using MAC address from net device See doc/README.enetaddr for details. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-14/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* net: fec: Avoid MX28 bus sync issueMarek Vasut2013-07-12-0/+22
| | | | | | | | | | | | | | | | | | The MX28 multi-layer AHB bus can be too slow and trigger the FEC DMA too early, before all the data hit the DRAM. This patch ensures the data are written in the RAM before the DMA starts. Please see the comment in the patch for full details. This patch was produced with an amazing help from Albert Aribaud, who pointed out it can possibly be such a bus synchronisation issue. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
* net: fec: Remove bogus flush_dcache_range() callMarek Vasut2013-07-12-1/+0
| | | | | | | | | | | | Remove incorrectly called and duplicate flush_dcache_range() call from fec_mxc driver. The call is not needed, since the caches are already flushed in fec_tbd_init(), moreover the second argument should be the ending address, not size. Signed-off-by: Marek Vasut <marex@denx.de> Reported-by: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
* net: fec_mxc: Add support for Vybrid VF610Alison Wang2013-06-03-3/+1
| | | | | | | | | | | | | | This patch adds FEC support for Vybrid VF610 platform. In function fec_open(), RCR register is only set as RGMII mode. But RCR register should be set as RMII mode for VF610 platform. This configuration is already done in fec_reg_setup(), so this piece of code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits. Signed-off-by: Alison Wang <b18965@freescale.com> Reviewed-by: Benoit Thebaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* net: fec_mxc: get phydev before fec_probeTroy Kisky2013-01-28-42/+75
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: only call phy_connect in fec_probeTroy Kisky2013-01-28-21/+12
| | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: use fec_set_dev_name to set nameTroy Kisky2013-01-28-8/+8
| | | | | | | This allows us to create the phydev before calling fec_probe in later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: have fecmxc_initialize call fecmxc_initialize_multiTroy Kisky2013-01-28-16/+8
| | | | | | | Having only one call to fec_probe will ease the changing of its parameters. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: change fec_mii_setspeed parameterTroy Kisky2013-01-28-5/+5
| | | | | | | | | | | | | Only the hardware ethernet registers are needed for this function, so don't pass the more general structure. I'm trying to separate MII and fec. This also fixes MX28 fec_mii_setspeed use on secondary ethernet port This was found by inspection of the code and should be checked on real hardware. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: delete CONFIG_FEC_MXC_MULTITroy Kisky2013-01-28-1/+1
| | | | | | | It is more logical to test for CONFIG_FEC_MXC_PHYADDR to determine whether to define the function fecmxc_initialize. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* FEC: Replace magic contantsMarek Vasut2012-09-27-3/+3
| | | | | | | | | | Replace the magic contant 1 << 24 with properly defined bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Rework the TX wait mechanismMarek Vasut2012-09-27-9/+11
| | | | | | | | | | | | | | | | | | | | | | | The mechanism waiting for transmission to finish in fec_send() now relies on the E-bit being cleared in the TX buffer descriptor. In case of data cache being on, this means invalidation of data cache above this TX buffer descriptor on each test for the E-bit being cleared. Apparently, there is another way to check if the transmission did complete. This is by checking the TDAR bit in the X_DES_ACTIVE register. Reading a register does not need any data cache invalidation, which is beneficial. Rework the sequence that wait for completion of the transmission so that the TDAR bit is tested first and afterwards check the E-bit being clear. This cuts down the number of cache invalidation calls to one. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Remove endless loop in the FEC driverMarek Vasut2012-09-27-1/+13
| | | | | | | | | | | | The FEC hardware sometimes errors out on data transfer and hangs in the tightloop adjusted by this patch. So add timeout into the tightloop to make such a hang recoverable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* FEC: Properly align address over the buffers for cache opsMarek Vasut2012-09-27-6/+8
| | | | | | | | | | Align the address that's to be invalidated/flushed properly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benoit Thebaudeau <benoit.thebaudeau@advans> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* FEC: Do not pass unaligned buffer to network stackMarek Vasut2012-09-27-1/+2
| | | | | | | | | | | | | | Do not pass unaligned RX buffer to the upper layers. The upper layer, especially in the ARP case, recycles the buffer and passes it back into the FEC, into it's TX path. With caches enabled, the FEC hangs on this from time to time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benoit Thebaudeau <benoit.thebaudeau@advans> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
* net: fec_mxc: Fix MDC for xMIIbenoit.thebaudeau@advans2012-07-19-1/+1
| | | | | | | | | The MDC signal is available on all xMII (i.e. 'not 7-wire') interfaces, so mii_speed has to be set for all these interfaces, and not only for MII. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* net: fec_mxc: Fix setting of RCR for xMIIbenoit.thebaudeau@advans2012-07-19-5/+3
| | | | | | | | | | | | | | | | | | At least on i.MX25, the RMII mode did not work, which is fixed by this patch. The MII_MODE bit of the FEC RCR register means xMII, i.e. 'not 7-wire', so set it accordingly. According to the xMII and 7-wire (aka GPSI) standards, full duplex should be available on xMII, but not on 7-wire, so set FCE accordingly. The FEC may support full duplex for 7-wire too, but the reference manual does not say that, so avoid an invalid assumption. Actually, the choice between half and full duplex also depends on the endpoint/switch/repeater configuration, so a config option could be added for that, but there has been no need for it so far. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
* net: abort network initialization if the PHY driver failsTimur Tabi2012-07-11-1/+7
| | | | | | | | | | Now that phy_startup() can return an actual error code, check for that error code and abort network initialization if the PHY fails. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Nobuhiro Iwamamatsu <nobuhiro.iwamatsu.yj@renesas.com> (sh_eth part) Acked-by: Stephan Linz <linz@li-pro.net> (Xilinx part, xilinx_axi_emac and xilinx_ll_temac) Reviewed-by: Marek Vasut <marex@denx.de> (FEC part)
* drivers/net/fec_mxc.c: Fix compile warningJoe Hershberger2012-05-22-1/+1
| | | | | | | | | Fix this: fec_mxc.c: In function 'fec_probe': fec_mxc.c:926:13: warning: assignment from incompatible pointer type Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com>
* FEC: Abstract out register setupMarek Vasut2012-05-15-46/+38
| | | | | | | | | | | Abstract out common register setup. This also configured r_cntrl to correct value at registration time. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* NET: fec_mxc.c: Add a way to disable auto negotiationStefano Babic2012-05-15-1/+3
| | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* net: fec_mxc: allow use with cache enabledEric Nelson2012-03-29-86/+191
| | | | | | | | | | | | | Ensure that transmit and receive buffers are cache-line aligned. Invalidate cache for each packet as received, update receive buffer descriptors one cache line at a time, flush cache before transmitting. Original patch by Marek: http://lists.denx.de/pipermail/u-boot/2012-February/117695.html Signed-off-by: Eric Nelson <eric.nelson at boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* net: fec_mxc: add PHYLIB supportTroy Kisky2012-02-27-48/+96
| | | | | | | | | | | | | | | | | | | | | Surround non PHYLIB routines miiphy_restart_aneg and miiphy_wait_aneg with ifndef CONFIG_PHYLIB. When later PHYLIB is required it is easy to delete the non-PHYLIB code. This separation idea came from Andy Fleming. fec_miiphy_read, and fec_miiphy_write changed to fec_phy_read, and fec_phy_write with argument changes. Deprecated miiphy_register is no longer used. Both old and new PHYLIB code now use mdio_register. Cleanup some debug prints. Inline function fec_miiphy_fec_to_eth is no longer necessary. Moved to the single call location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* net: fec_mxc: add 1000 Mbps selectionTroy Kisky2012-02-27-2/+19
| | | | | | | | Define FEC_QUIRK_ENET_MAC and add to arch-mx6/imx-regs.h Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
* net: imx: Add multi-FEC support for imx_get_mac_from_fuseFabio Estevam2012-01-16-4/+5
| | | | | | | | | | Add multi-FEC support for imx_get_mac_from_fuse by passing dev_id as a parameter. This feature is important on mx28 SoC for example that has two FEC ports. Cc: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* fec: add the i.mx6q enet driver supportJason Liu2012-01-16-0/+10
| | | | | | Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jason Liu <jason.hui@linaro.org> Acked-by: Stefano Babic <sbabic@denx.de>
* FEC: Add support for iMX28 quirksMarek Vasut2011-11-11-2/+42
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* GCC4.6: Squash warnings in fec_mxc.cMarek Vasut2011-10-27-2/+2
| | | | | | | | | | | | | | fec_mxc.c: In function 'fec_mii_setspeed': fec_mxc.c:112:2: warning: format '%#lx' expects type 'long unsigned int', but argument 2 has type 'u32' fec_mxc.c: In function 'fec_recv': fec_mxc.c:632:2: warning: format '%x' expects type 'unsigned int', but argument 2 has type 'long unsigned int' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* FEC: Squish "got MAC from fuse" message, make it debug()Marek Vasut2011-09-30-1/+1
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Add timeout for chip resetMarek Vasut2011-09-30-4/+21
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Allow registering MII postconfiguration callbackMarek Vasut2011-09-30-1/+13
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Allow multiple FECesMarek Vasut2011-09-30-30/+49
| | | | | | | | | | | | | | | | | | | This patch allows user to register multiple FEC controllers. To preserve compatibility with older boards, the mxcfec_register() call is still in place. To use multiple controllers, new macro is in place, the mxcfec_register_multi(), which takes more arguments. The syntax is: mxcfec_register_multi(bd, FEC ID, FEC PHY ID on the MII bus, base address); To disable the fecmxc_register() compatibility stuff, define the macro CONFIG_FEC_MXC_MULTI. This will remove the requirement for defining IMX_FEC_BASE and CONFIG_FEC_MXC_PHYADDR. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Abstract access to fec->eth in MII operationsMarek Vasut2011-09-30-8/+10
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Allow selection of MII mode via CONFIG_FEC_XCV_TYPEMarek Vasut2011-09-30-1/+5
| | | | | | | | | | The default is MII100, which was hardcoded previously in the driver. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Add RMII mode supportMarek Vasut2011-09-30-0/+2
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Kill mode select FIXME'sMarek Vasut2011-09-30-12/+14
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Use defined constant instead of magic numberMarek Vasut2011-09-30-1/+1
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* FEC: Use proper accessor to read register in debug callMarek Vasut2011-09-30-1/+1
| | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Ben Warren <biggerbadderben@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de>
* Timer: Fix misuse of ARM *timer_masked() functions outside arch/armGraeme Russ2011-07-16-3/+3
| | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* fec_mxc: add support for MX53 processorLiu Hui-R643432011-02-02-1/+1
| | | | | | This patch add FEC support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-10/+10
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* imx: Get fec mac address from fuseLiu Hui-R643432010-11-21-15/+2
| | | | | | | The patch is to support getting FEC MAC address from fuse bank. Signed-off-by: Jason Liu <r64343@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de>
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