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path: root/drivers/net/designware.c
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* net: dwc: Make the cache handling less crypticMarek Vasut2014-10-06-25/+23
| | | | | | | | | | | | | | | | | Add a few new variables to make the cache handling less cryptic. Add a variable for DMA and DATA descriptor start and end, so the correctness of the code is easier to inspect. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* net: dwc: Fix cache alignment issuesMarek Vasut2014-10-06-2/+4
| | | | | | | | | | | | | | | | | Fix remaining cache alignment issues in the DWC Ethernet driver. Please note that the cache handling in the driver is making the code hideous and thus the next patch cleans that up. In order to make this change reviewable though, the cleanup is split from it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Pavel Machek <pavel@denx.de>
* net/designware: Make DMA burst length configurable and reduce by defaultIan Campbell2014-05-25-1/+1
| | | | | | | | | | | The correct value for this setting can vary across SoCs and boards, so make it configurable. Also reduce the default value to 8, which is the same default as used in the Linux driver. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGNIan Campbell2014-05-25-5/+13
| | | | | | | | | | | This is required at least on ARM. When sending instead of simply invalidating the entire descriptor, flush as little as possible while still respecting ARCH_DMA_MINALIGN, as requested by Alexey. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: ensure device private data is DMA aligned.Ian Campbell2014-05-25-1/+2
| | | | | | | | | | struct dw_eth_dev contains fields which are accessed via DMA, so make sure it is aligned to a dma boundary. Without this I see: ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0 Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Marek Vasut <marex@denx.de>
* net/designware: call phy_connect_dev() to properly setup phylib deviceIan Campbell2014-05-12-0/+2
| | | | | | | | | | | This sets up the linkage from the phydev back to the ethernet device. This symptom of not doing this which I noticed was: <NULL> Waiting for PHY auto negotiation to complete.... rather than: dwmac.1c50000 Waiting for PHY auto negotiation to complete.... Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
* net/designware: make driver compatible with data cacheAlexey Brodkin2014-02-07-3/+50
| | | | | | | | | | | | | | | | | | | | Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware - switch driver to phylib usageAlexey Brodkin2014-02-07-311/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net/designware: add explicit reset of {tx|rx}_currdescnumAlexey Brodkin2014-02-07-0/+2
| | | | | | | | | | | | | | | | | | Driver "init" function might be called multiple times. On every "init" Tx/Rx buffer descriptors are initialized: "descs_init" -> "{tx|rx}_descs_init". In its turn those init functions set MAC's "{tx|rx}desclistaddr" to point on the first buffer descriptor in the list. So CPU to start operation from the first buffer descriptor as well after every "init" we have to reset "{tx|rx}_currdescnum". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* net: designware: Respect "bus mode" register contents on SW resetAlexey Brodkin2013-11-22-1/+1
| | | | | | | | | | | | "bus mode" register contains lots of fields and some of them don't expect to be written with 0 (zero). So since we're only interested in resetting MAC (which is done with setting the least significant bit of this register with "0") I believe it's better to modify only 1 bit of the register. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Vipin Kumar <vipin.kumar@st.com> Patch: 277864
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* net/designware: Do not select MIIPORT for RGMII interfaceVipin Kumar2013-06-24-1/+3
| | | | | | | Do not select MIIPORT for RGMII interface Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de>
* net/designware: Consecutive writes to the same register to be avoidedDinh Nguyen2012-07-11-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Matthew Gerlach <mgerlach@altera.com> Acked-by: Amit Virdi <amit.virdi@st.com>
* net: Multiple updates/enhancements to designware.cStefan Roese2012-07-07-69/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the following changes to designware ethernet driver found on the ST SPEAr SoC: - Don't init MAC & PHY upon startup. This causes a delay, waiting for the auto negotiation to complete. And we don't want this delay to always happen. Especially not on platforms where ethernet is not used at all (e.g. booting via flash). Instead postpone the MAC / PHY configuration to the stage, where ethernet is first used. - Add possibility for board specific PHY init code. This is needed for example on the X600 board, where the Vitesse PHY needs to be configured for GMII mode. This board specific PHY init is done via the function designware_board_phy_init(). And this driver now adds a weak default which can be overridden by board code. - Use common functions miiphy_speed() & miiphy_duplex() to read link status from PHY. - Print status and progress of auto negotiation. - Print link status (speed, dupex) upon first usage. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
* SPEAr: Add interface information in initializationVipin Kumar2012-07-07-1/+9
| | | | | | | | | | Few Designware peripheral registers need to be modified based on the ethernet interface selected by the board. This patch supports interface information in ethernet driver Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
* net: Fix remaining API interface breakageJoe Hershberger2012-05-23-3/+2
| | | | | | | | | | | These are all the files which use the API incorrectly but did not get built using MAKEALL -a powerpc|arm. I have no compiler for them, but the remaining issues should be far less than without this patch. Any outstanding issues are left to the maintainers of boards that use these drivers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* net/designware: Change timeout loop implementationAmit Virdi2012-04-04-16/+38
| | | | | | | The new implementation changes the timeout loop implementation to avoid 1 ms delay in each failing test. It also configures the delay to 10usec. Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Set ANAR to 0x1e1Armando Visconti2012-04-04-0/+3
| | | | | | | | This patch forces the advertised capabilities during auto negotiation to always be 10/100 Mbps and half/full as duplexing. Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Program phy registers when auto-negotiation is ONVikas Manocha2012-04-04-14/+29
| | | | | | | | | | If AN(auto-negotiation) is ON, speed bit of control register are not applicable. Also phy registers were not getting programmed as per the result of AN. This patch sets only AN bit & restart AN bit for AN ON selection & programs PHY registers as per AN result. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Try configuring phy on each dw_eth_initVipin Kumar2012-04-04-21/+29
| | | | | | | | | | | | | Phy autonegotiation works only when the ethernet cable is plugged in. Since the phy was configured only at the init time, a plugged in cable was necessary to initialize the phy properly. This patch keeps a flag to check if the phy initialization has succeeded, and calls configure_phy routine at every init if this flag reports otherwise. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Consecutive writes must have delayArmando Visconti2012-04-04-2/+1
| | | | | | | | | This patch solves a TX/RX problem which happens at 10Mbps, due to the fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between two consecutive writes on the same register. Signed-off-by: Armando Visconti <armando.visconti@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Phy address fixVipin KUMAR2012-04-04-1/+1
| | | | | | | | The code assumes the phy address to be > 0, which is not true, the phy address can be in the range 0-31. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* net/designware: Fix to restore hw mac addressVipin KUMAR2012-04-04-1/+6
| | | | | | | | | The network controller mac resets hardware address stored in MAC_HI and MAC_LO registers if mac is resetted. So, hw mac address needs to be restored in case mac is explicitly resetted from driver. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com>
* Add Ethernet hardware MAC address framework to usbnetSimon Glass2011-08-08-1/+1
| | | | | | | | | | | | Built-in Ethernet adapters support setting the mac address by means of a ethaddr environment variable for each interface (ethaddr, eth1addr, eth2addr). This adds similar support to the USB network side, using the names usbethaddr, usbeth1addr, etc. They are kept separate since we don't want a USB device taking the MAC address of a built-in device or vice versa. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Eric Bénard <eric@eukrea.com>
* net: designware: fix uninitialized phy_addr usageMike Frysinger2011-07-25-0/+2
| | | | | | | | | | | | When CONFIG_DW_SEARCH_PHY is disabled, the local phy_addr variable never gets initialized which causes random behavior at runtime and a gcc warning. So set it by default to the stored phy address. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Fix commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
* net: designware: fix unused warning when CONFIG_DW_AUTONEG is enabledMike Frysinger2011-07-25-1/+3
| | | | | | | | The ctrl variable is only used when autoneg support is disabled, so only declare it under those conditions to avoid an unused variable warning. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
* miiphy: convert to linux/mii.hMike Frysinger2011-01-09-27/+27
| | | | | | | | The include/miiphy.h header duplicates a lot of things from linux/mii.h. So punt all the things that overlap to keep the API simple and to make merging between U-Boot and Linux simpler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* miiphy: constify device nameMike Frysinger2010-08-09-2/+2
| | | | | | | The driver name does not need to be writable, so constify it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* SPEAr : Network driver support addedVipin KUMAR2010-07-12-0/+531
Designware network driver support added. This is a Synopsys ethernet controller Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
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