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* nand_spl_simple: Add a simple NAND read functionThomas Gleixner2016-07-22-0/+62
| | | | | | | | | | | To support UBI in SPL we need a simple NAND read function. Add one to nand_spl_simple and keep it as simple as it goes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+24
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* mtd: cfi_flash: fix polling for bit XSR.7 on Intel chipsDaniel Schwierzeck2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-2/+2
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Drop a blank line in nand_wait()Andre Renaud2016-06-24-1/+0
| | | | | | | This empty line should not be there. Remove it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-06-20-180/+333
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| * mtd: nand: Patch remaining places where nand_to_mtd() should be usedBoris Brezillon2016-06-19-5/+5
| | | | | | | | | | | | | | Some drivers are still directly accessing the chip->mtd field. Patch them to use nand_to_mtd() instead. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * nand: nand torture: follow sync with linux v4.6Max Krummenacher2016-06-19-1/+1
| | | | | | | | | | | | follow parameter name change (nand to mtd) to fix compiler error. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * spl: nand: sunxi: add support for NAND config auto-detectionBoris Brezillon2016-06-19-58/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND chips are supposed to expose their capabilities through advanced mechanisms like READID, ONFI or JEDEC parameter tables. While those methods are appropriate for the bootloader itself, it's way to complicated and takes too much space to fit in the SPL. Replace those mechanisms by a dumb 'trial and error' mechanism. With this new approach we can get rid of the fixed config list that was used in the sunxi NAND SPL driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: split 'load page' and 'read page' logicBoris Brezillon2016-06-19-71/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the 'load page' and 'read page' logic in 2 different functions so we can later load the page and test different ECC configs without the penalty of reloading the same page in the NAND cache. We also move common setup to a dedicated function (nand_apply_config()) to avoid rewriting the same values in NFC registers each time we read a page. These new functions are passed a pointer to an nfc_config struct to limit the number of parameters. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: rework status polling loopBoris Brezillon2016-06-19-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | check_value_xxx() helpers are using a 1ms delay between each test, which can be quite long for some operations (like a page read on an SLC NAND). Since we don't have anything to do but to poll this register, reduce the delay between each test to 1us. While we're at it, rename the max_number_of_retries parameters and the MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that we're actually waiting a given amount of time and not only a number of retries. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: stop guessing the redundant u-boot offsetBoris Brezillon2016-06-19-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess where the redundant u-boot image is based on simple (and most of the time erroneous) heuristics. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> # Conflicts: # drivers/mtd/nand/sunxi_nand_spl.c
| * spl: nand: support redundant u-boot imageBoris Brezillon2016-06-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On modern NAND it's more than recommended to have a backup copy of the u-boot binary to recover from corruption: bitflips are quite common on MLC NANDs, and the read-disturbance will corrupt your u-boot partitition more quickly than what you would see on an SLC NAND. Add an extra Kconfig option to specify the offset of the redundant u-boot image. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> [scottwood: added ifdef to fix build break] Signed-off-by: Scott Wood <oss@buserror.net>
| * spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependencyBoris Brezillon2016-06-19-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced to explicitly depend on platforms that are not already defining it in their include/configs/<board>.h header. Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS depends on it, remove the dependency on NAND_SUNXI and make it dependent on SPL selection. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: remove support for so-called 'syndrome' modeBoris Brezillon2016-06-19-42/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi SPL NAND controller driver supports use 'BootROM'-like configs, that is, configs where the ECC bytes and real data are interleaved in the page instead of putting ECC bytes in the OOB area. Doing that has several drawbacks: - since you're interleaving data and ECC bytes you can't use the whole page otherwise you might override the bad block marker with non-FF bytes. - to solve the bad block marker problem, the ROM code supports partially using the page, but this introduces a huge penalty both in term of read speed and NAND memory usage. While this is fine for rather small binaries(like the SPL one which is at maximum 24KB large), it becomes non-negligible for the bootloader image (several hundred of KB). - auto-detection of the page size is not reliable (this is in my opinion the biggest problem). If you get the page size wrong, you'll end up reading data at a different offset than what was specified by the caller and the reading may succeed (if valid data were written at this address). For all those reasons I think it's wiser to completely remove support for 'syndrome' configs. If we ever need to support it again, then I'd recommend specifying all the config parameters through Kconfig options. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-13-2/+3
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| * | at91: nand: Set up the ECC strength correctlyAndre Renaud2016-06-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This needs to be set to avoid a fatal error when ECC is used. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | at91: Correct NAND ECC register accessAndre Renaud2016-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This uses the wrote base register value. Fix it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-1/+1
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| * | mtd: nand: mxs: use simpler runtime cpu dection macrosPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Scott Wood <oss@buserror.net>
* | | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-09-0/+4
| | | | | | | | | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | nand: add nand mtd concat supportHeiko Schocher2016-06-09-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | add for nand devices mtd concat support. Generic MTD concat support is already ported to mainline, and used in the cfi_mtd driver. This patch adds it similiar for nand devices. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-06-04-2247/+876
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| * | nand: fix nand torture to use changed mtd apiMax Krummenacher2016-06-03-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mtd subsystem deprecated and renamed the direct use of the mtd_info struct's functionpointers. Instead the corresponding mtd_xxx function should be used. See also: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * | mtd: nand: Sync with Linux v4.6Scott Wood2016-06-03-171/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates the NAND code to match Linux v4.6. The previous sync was from Linux v4.1 in commit d3963721d93fafa. Note that none of the individual NAND drivers tracked Linux closely enough to be synced themselves, other than manually applying a few cross-tree changes. Signed-off-by: Scott Wood <oss@buserror.net> Tested-by: Heiko Schocher <hs@denx.de>
| * | mtd: nand: Add page argument to write_page() etc.Scott Wood2016-06-03-46/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change is part of the Linux 4.6 sync. It is being done before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood2016-06-03-307/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
| * | nand: Embed mtd_info in struct nand_chipScott Wood2016-06-03-165/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Remove nand_info_t typedefScott Wood2016-06-03-90/+90
| | | | | | | | | | | | | | | | | | | | | This typedef serves no purpose other than causing confusion with struct nand_chip. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Remove docg4 driver and palmtreo680 flashing toolScott Wood2016-06-03-1251/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only user of the docg4 driver and the palmtreo680 image flashing tool. This patch removes them. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Mike Dunn <mikedunn@newsguy.com> Cc: Simon Glass <sjg@chromium.org>
| * | mtd: nand: Remove jz4740 driverMarek Vasut2016-06-03-259/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is not used by anyone, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Scott Wood <oss@buserror.net> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: arasan_nfc: Correct nand ecc initializationSiva Durga Prasad Paladugu2016-06-03-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the nand ecc initialization code This fixes the issue of incorrect nand ecc init if no device is found in ecc_matrix then it endsup ecc init with junk initialization instead of the most suited one. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
* | | driver: mtd: spi: Adding support for QSPI flashPrabhakar Kushwaha2016-06-03-2/+4
|/ / | | | | | | | | | | | | | | | | | | | | Serial number, vendor id and page size are added for QSPI flash common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mtd: nand: am335x: spl: Fix copying of imageLokesh Vutla2016-05-27-1/+14
| | | | | | | | | | | | | | | | | | When offset is not aligned to page address, it is possible that extra offset will be read from nand. Adjust the image such that first byte of the image is at load address after the first page is read. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | spl: Support loading a FIT from SPILokesh Vutla2016-05-27-5/+32
| | | | | | | | | | | | | | | | Detect a FIT when loading from SPI and handle it using the new FIT SPL support. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-24-0/+77
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| * sf: Disable 4-KB erase command for SPANSION S25FS-S familyYuan Yao2016-05-18-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-18-0/+5
| | | | | | | | | | | | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | drivers: mtd: add Microchip PIC32 internal non-CFI flash driver.Purna Chandra Mandal2016-05-21-0/+452
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIC32 internal flash devices are parallel NOR flash divided into number of banks to allow erase-programming in one while fetch and execution continues on other. As the flash banks are memory mapped stored code can be executed directly from flash (XIP), also there is additional hardware logic to prefetch and cache contents to improve execution performance. These flash can also be used to store user data (like environment). Flash erase and programming are handled by on-chip NVM controller. Driver implemented driver model but MTD is not really support. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | SPL: Let spl_parse_image_header() return valueMarek Vasut2016-05-17-2/+8
|/ | | | | | | | | | | Allow the spl_parse_image_header() to return value. This is convenient for controlling the SPL boot flow if the loaded image is corrupted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com>
* Fix spelling of "occurred".Vagrant Cascadian2016-05-02-2/+2
| | | | | Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* sf: fix timebase data type in _wait_ready()Stephen Warren2016-04-25-1/+2
| | | | | | | | | | | | | | get_timer() returns an unsigned 64-bit value, but is currently assigned to a signed 32-bit variable. Due to sign extension and data truncation, this causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and incorrectly) fire for about 50% of all time values, based on whether bit 31 is set. In sandbox at least, this causes the test to pass or fail based on system uptime, as opposed to time since the U-Boot binary was started. Fixes: 4efad20a1751 ("sf: Update status reg check in spi_flash_cmd_wait_ready") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mtd, ubi: set free_count to zero before walking through erase listHeiko Schocher2016-04-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | Set free_count to zero before walking through ai->erase list in wl_init(). As U-Boot has no workqueue/threads, it immediately calls erase_worker(), which increase for each erased block free_count. Without this patch, free_count gets after this initialized to zero in wl_init(), so the free_count variable always has the maybe wrong value 0. Detected this behaviour on the dxr2 board, where the UBI fastmap gets not written when attaching/dettaching on an empty NAND. It drops instead the error message: could not find any anchor PEB With this patch, fastmap gets written on dettach. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* mtd: cfi: Unlock current sector instead of sector 0 before buffered writeRouven Behr2016-04-13-1/+1
| | | | | | | | | Unlock current sector instead of sector 0 before buffered write. [Patch subject and commit text slightly reworded, Stefan] Signed-off-by: Rouven Behr <u-boot@behr-iss.de> Signed-off-by: Stefan Roese <sr@denx.de>
* stm32: stm32_flash: add memory barrier during flash writeVikas Manocha2016-04-11-0/+4
| | | | | | | | After writing data to flash space, next instruction is checking if flash controller is busy writing to the flash memory. Memory barrier is required here to avoid transaction re-ordering for data write and busy status check. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* drivers: remove writes{b,w,l,q} and reads{b,w,l,q}.Purna Chandra Mandal2016-04-10-8/+0
| | | | | | | Definition of writes{bwlq}, reads{bwlq} are now added into arch specific asm/io.h. So removing them from driver to fix re-definition error Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
* kirkwood_nand: claim MPP pins on the flyChris Packham2016-04-06-0/+19
| | | | | | | | | | | Claim the MPP pins for the NAND flash controller only when it's actually being used. This allows the pins to be shared with the SPI interface which already supports an equivalent on-access MPP reconfiguration. Reviewed-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Scott Wood <oss@buserror.net> Signed-off-by: Stefan Roese <sr@denx.de>
* mtd: nand: denali: max_banks calculation changed in revision 5.1Graham Moore2016-04-01-1/+12
| | | | | | | | | | | | | | Read Denali hardware revision number and use it to calculate max_banks, The encoding of max_banks changed in Denali revision 5.1. [ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ] Signed-off-by: Graham Moore <grmoore@opensource.altera.com> [Brian: parentheses around macro arg] Signed-off-by: Brian Norris <computersforpeace@gmail.com> [Masahiro: import from Linux and adjust ioread32() to readl() ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* cfi_flash: return device into read array mode after reading statusVasily Khoruzhick2016-03-27-0/+2
| | | | | | | | Otherwise flash remains in read status mode and it's not possible to access data on flash. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-07 09:45:59 +0000