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* sandbox: spi: Add newline to printf() in sandbox_sf_probeSimon Glass2015-05-14-1/+1
| | | | | | | | This printf() should have a newline at the end. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dm: sf: Update default name of spi flash in structure udeviceHaikun.Wang@freescale.com2015-05-06-2/+2
| | | | | | | Default name of spi flash like this "0:0", update it to "spi_flash@0:0". Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-04-28-42/+46
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| * sf: Fix to compute proper sector_sizeJagannadha Sutradharudu Teki2015-04-28-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upto now flash sector_size is assigned from params which isn't necessarily a sector size from vendor, so based on the SECT_* flags from flash_params the erase_size will compute and it will become the sector_size finally. Bug report (from Bin Meng): => sf probe SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB, total 2 MiB, mapped at ffe00000 => sf erase 0 +100 SF: 65536 bytes @ 0x0 Erased: OK Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reported-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: sf: Make SST flash write op work againBin Meng2015-04-28-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | With SPI flash moving to driver model, commit fbb0991 "dm: Convert spi_flash_probe() and 'sf probe' to use driver model" ignored the SST flash-specific write op (byte program & word program), which actually broke the SST flash from wroking. This commit makes SST flash work again under driver model, by adding SST flash-specific handling in the spi_flash_std_write(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: Save flash flags to struct spi_flashBin Meng2015-04-28-0/+3
| | | | | | | | | | | | | | | | Add a new member 'flags' in struct spi_flash to store the flash flags during spi_flash_validate_params(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * Revert "spi: add config option to enable the WP pin function on st micron ↵Jagannadha Sutradharudu Teki2015-04-23-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | flashes" This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Heiko Schocher <hs@denx.de>
| * mtd: spi: check return value of spi_setup_slavePeng Fan2015-04-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to check value of spi_setup_slave and spi_setup_slave_fdt. If their return value 'bus' is NULL, there is no need to pass it to following spi_flash_probe_tail. If 'bus' is null, the original function flow is as following: spi_flash_probe |->spi_setup_slave |->spi_probe_bus_tail |->spi_flash_probe_slave |->spi_free_slave Alougth check the pointer in spi_free_slave is ok, checking the return value of spi_setup_slave and spi_setup_slave_fdt is better. Before this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! SF: Failed to set up slave data abort pc : [<fff66dcc>] lr : [<fff7628c>] reloc pc : [<87814dcc>] lr : [<8782428c>] sp : fdf4fcf0 ip : e630396c fp : fe0d0888 r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00 r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... " After this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! Failed to initialize SPI flash at 0:2 " No data abort using this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Poll both the read status and flag statusSiva Durga Prasad Paladugu2015-04-22-7/+25
| | | | | | | | | | | | | | | | | | Poll both the Read status and Flag status registers for sucessful erase and program operations for the Micron devices with E_FSR flag set in params table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-1/+1
| | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-24/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | nand/fsl_ifc: Increase eccstat[] for IFC 2.0Scott Wood2015-04-23-2/+9
|/ | | | | | | | IFC 2.0 doubled the SRAM size, which means double the number of ECCSTAT registers. Fix the resulting array overflow. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* sandbox: Move CONFIG_SPI_FLASH_SANDBOX to KconfigSimon Glass2015-04-18-0/+10
| | | | | | Move this over to Kconfig and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: spi_flash: fix wrong dependencyMasahiro Yamada2015-04-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | CONFIG_SPI does not exist in Kconfig in the first place, so the dependency "depends on DM && SPI" is never met, i.e., DM_SPI_FLASH can never be enabled (unless you ignore the dependency in an illegal way. See below.) Actually, some defconfigs such as socfpga_*_defconfig define CONFIG_DM_SPI_FLASH=y, but it never appears in the .config file because of this wrong dependency. On the other hand, all the Tegra boards enable DM_SPI_FLASH because config DM_SPI_FLASH default y silently ignores the dependency. Unfortunately, this style of CONFIG definition is abused everywhere in U-Boot, so we easily miss such a wrong dependency. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: sf: Add driver model read/write/erase methodsSimon Glass2015-04-18-0/+16
| | | | | | | | Permit use of a udevice to talk to SPI flash. Ultimately we would like to retire the use of 'struct spi_flash' for this purpose, so create the new API for those who want to move to it. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Make sure arch-specific map_sysmem() is definedJoe Hershberger2015-04-18-0/+1
| | | | | | | | | | | In the case where the arch defines a custom map_sysmem(), make sure that including just mapmem.h is sufficient to have these functions as they are when the arch does not override it. Also split the non-arch specific functions out of common.h Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: core: Add dev_get_uclass_priv() to access uclass private dataSimon Glass2015-04-16-5/+5
| | | | | | | | Add a convenience function to access the private data that a uclass stores for each of its devices. Convert over most existing uses for consistency and to provide an example for others. Signed-off-by: Simon Glass <sjg@chromium.org>
* lpc32xx: mtd: nand: add MLC NAND controllerAlbert ARIBAUD \(3ADEV\)2015-04-10-0/+765
| | | | | | | | | | The controller's Reed-Solomon ECC hardware is used except of course for raw reads and writes. It covers in- and out-of-band data together. The SPL framework is supported. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-03-31-0/+6
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| * ARM: at91: atmel_nand: Support flash based BBTDavid Dueck2015-04-01-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for on-flash bad block table. This makes U-Boot handle an existing BBT correctly. Signed-off-by: David Dueck <davidcdueck@googlemail.com> Reviewed-by: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Boris BREZILLON <boris.brezillon@free-electrons.com> CC: Josh Wu <josh.wu@atmel.com> CC: Andreas Bießmann <andreas.devel@googlemail.com> CC: Scott Wood <scottwood@freescale.com> Acked-by: Josh Wu <josh.wu@atmel.com>
* | mtd: vf610_nfc: specify transfer size before each transferStefan Agner2015-03-30-8/+17
| | | | | | | | | | | | | | | | | | | | Testing showed, that commands like STATUS made the buffer dirty when executed with NFC_SECSZ set to the page size. It looks like the controller transfers bogus data when this register is configured. When setting it to 0, the buffer does not get altered while the status command still seems to work flawless. Signed-off-by: Stefan Agner <stefan@agner.ch>
* | mtd: vf610_nfc: mark page as dirty on block eraseStefan Agner2015-03-30-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver tries to re-use the page buffer by storing the page number of the current page in the buffer. The page is only read if the requested page number is not currently in the buffer. When a block is erased, the page number is marked as invalid if the erased page equals the one currently in the cache. However, since a erase block consists of multiple pages, also other page numbers could be affected. The commands to reproduce this issue (on a written page): > nand dump 0x800 > nand erase 0x0 0x20000 > nand dump 0x800 The second nand dump command returns the data from the buffer, while in fact the page is erased (0xff). Avoid the hassle to calculate whether the page is affected or not, but set the page buffer unconditionally to invalid instead. Signed-off-by: Stefan Agner <stefan@agner.ch>
* | nand: yaffs: Remove the "nand write.yaffs" commandPeter Tyser2015-03-30-65/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This command is only enabled by one board, complicates the NAND code, and doesn't appear to have been functioning properly for several years. If there are no bad blocks in the NAND region being written nand_write_skip_bad() will take the shortcut of calling nand_write() which bypasses the special yaffs handling. This causes invalid YAFFS data to be written. See http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for an example and a potential workaround. U-Boot still retains the ability to mount and access YAFFS partitions via CONFIG_YAFFS2. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser2015-03-30-248/+0
| | | | | | | | | | | | | | | | | | The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | nand: Add verification functionsPeter Tyser2015-03-30-1/+96
| | | | | | | | | | | | | | | | | | | | Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies NAND contents against an arbitrarily sized buffer using ECC while nand_verify_page_oob() verifies a NAND page's contents and OOB. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_write_buf()Luca Ellero2015-03-30-1/+1
| | | | | | | | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
* | mtd: nand: mxs: fix PIO_WORDs in mxs_nand_read_buf()Luca Ellero2015-03-30-1/+1
|/ | | | | | There is only one pio_word in this DMA transaction so data field must be 1. Signed-off-by: Luca Ellero <luca.ellero@brickedbrain.com>
* omap: gpmc: 'nandecc sw' can use HAM1 or BCH8Ash Charles2015-03-05-1/+11
| | | | | | | | | | | | | | | The 'nandecc sw' command selects a software-based error correction algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their software-based correction algorithm. Allow a user to be specific e.g. # nandecc sw <hamming|bch8> where 'hamming' is still the default. Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set to a hardware-based ECC scheme---a little strange when the user has requested 'sw' ECC. Signed-off-by: Ash Charles <ashcharles@gmail.com>
* mtd: nand: omap_gpmc: Make ready/busy pins configurableMichal Sojka2015-03-05-2/+14
| | | | | | | | | | | | | | | | | | | | | | | Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of WAIT0 pin for determining whether the NAND is ready or not. This only works if all NAND chips are connected to WAIT0. If some chips are connected to the other available pin WAIT1, nand_wait() does not really wait and prints a WARN_ON message. This patch allows the board to provide configuration of which chip is connected to which WAITx signal. For example, one can define in include/configs/foo.h: #define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1 This would mean that chips using to CS0 and 1 are connected to WAIT0 and chips with CS2 and 3 are connected to WAIT1. Signed-off-by: Michal Sojka <sojka@merica.cz> Acked-by: Stefan Roese <sr@denx.de> Tested-by: Michal Vokáč <michal.vokac@comap.cz> Cc: Tom Rini <trini@ti.com>
* kconfig: remove unneeded dependency on !SPL_BUILDMasahiro Yamada2015-02-24-4/+0
| | | | | | | Now CONFIG_SPL_BUILD is not defined in Kconfig, so "!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* kconfig: switch to single .config configurationMasahiro Yamada2015-02-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When Kconfig for U-boot was examined, one of the biggest issues was how to support multiple images (Normal, SPL, TPL). There were actually two options, "single .config" and "multiple .config". After some discussions and thought experiments, I chose the latter, i.e. to create ".config", "spl/.config", "tpl/.config" for Normal, SPL, TPL, respectively. It is true that the "multiple .config" strategy provided us the maximum flexibility and helped to avoid duplicating CONFIGs among Normal, SPL, TPL, but I have noticed some fatal problems: [1] It is impossible to share CONFIG options across the images. If you change the configuration of Main image, you often have to adjust some SPL configurations correspondingly. Currently, we cannot handle the dependencies between them. It means one of the biggest advantages of Kconfig is lost. [2] It is too painful to change both ".config" and "spl/.config". Sunxi guys started to work around this problem by creating a new configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add %_felconfig rule to enable FEL build of sunxi platforms.) added "make *_felconfig" to enable CONFIG_SPL_FEL on both images. Changing the configuration of multiple images in one command is a generic demand. The current implementation cannot propose any good solution about this. [3] Kconfig files are getting ugly and difficult to understand. Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files. [4] The build system got more complicated than it should be. To adjust Linux-originated Kconfig to U-Boot, the helper script "scripts/multiconfig.sh" was introduced. Writing a complicated text processor is a shell script sometimes caused problems. Now I believe the "single .config" will serve us better. With it, all the problems above would go away. Instead, we will have to add some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM, but we will not have much. Anyway, this is what we do now in scripts/Makefile.spl. I admit my mistake with my apology and this commit switches to the single .config configuration. It is not so difficult to do that: - Remove unnecessary processings from scripts/multiconfig.sh This file will remain for a while to support the current defconfig format. It will be removed after more cleanups are done. - Adjust some makefiles and Kconfigs - Add some entries to include/config_uncmd_spl.h and the new file scripts/Makefile.uncmd_spl. Some CONFIG options that are not supported on SPL must be disabled because one .config is shared between SPL and U-Boot proper going forward. I know this is not a beautiful solution and I think we can do better, but let's see how much we will have to describe them. - update doc/README.kconfig More cleaning up patches will follow this. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* mtd, omap: fix case NAND_OMAP_GPMC_PREFETCH not definedEgli, Samuel2015-02-16-1/+4
| | | | | | | | | | | | | | | | The patch c316f577b4b72d1a1aeb559e9b3fad20808f1ffd breaks siemens boards because prefetch mode is not enabled. I assume it breaks other boards as well that don't use prefetch. This patch sets read_buf to nand_read_buf if NAND_OMAP_GPMC_PREFETCH is not defined. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> CC: Daniel Mack <zonque@gmail.com> CC: Guido Martínez <guido@vanguardiasur.com.ar> CC: Tom Rini <trini@ti.com> CC: Heiko Schocher <hs@denx.de>
* dm: Expand and complete Kconfig in drivers/Simon Glass2015-02-12-0/+16
| | | | | | | | Expand the help messages for each driver. Add missing Kconfig for I2C, SPI flash and thermal. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* mtd: atmel_nand: according to pmecc version to perform 0xff page correctionWu, Josh2015-02-07-0/+29
| | | | | | | | | | | | As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini2015-02-04-0/+8
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| * ubi: reset mtd_devs when ubi part failHeiko Schocher2015-01-28-0/+8
| | | | | | | | | | | | | | if "ubi part" fails, reset also mtd_devs to 0, as further "ubi part" would use wrong mtd_devs. Signed-off-by: Heiko Schocher <hs@denx.de>
* | dm: spi: Move slave details to child platdataSimon Glass2015-01-29-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we go through various contortions to store the SPI slave's chip select in its private data. This only exists when the slave is active so must be set up when it is probed. Until the device is probed we don't actually know what chip select it will appear on. However, now that we can support per-child platform data, we can use that instead. This allows us to set up the chip select when the child is bound, and avoid the messy contortions. Unfortunately this is a fairly large change and it seems to be difficult to break it down further. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: sandbox: sf: Tidy up the error handling in sandbox_sf_probe()Simon Glass2015-01-29-2/+5
| | | | | | | | | | | | Use a single exit point when we have an error and add debugging there. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: tegra: nand: Remove use of fdtdec GPIO supportSimon Glass2015-01-29-5/+4
|/ | | | | | These functions are going away, so use the new uclass support instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boardsMasahiro Yamada2015-01-23-5/+0
| | | | | | | | | | | These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
* mtd: OMAP: Enable GPMC prefetch modeDaniel Mack2015-01-13-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | Enable GPMC's prefetch feature for NAND access. This speeds up NAND read access a lot by pre-fetching contents in the background and reading them through the FIFO address. The current implementation has two limitations: a) it only works in 8-bit mode b) it only supports read access Both is easily fixable by someone who has hardware to implement it. Note that U-Boot code uses non word-aligned buffers to read data into, and request read lengths that are not multiples of 4, so both partial buffers (head and tail) have to be addressed. Tested on AM335x hardware. Tested-by: Guido Martínez <guido@vanguardiasur.com.ar> Reviewed-by: Guido Martínez <guido@vanguardiasur.com.ar> Signed-off-by: Daniel Mack <zonque@gmail.com> [trini: Make apply again, use 'cs' fix pointed out by Guido] Signed-off-by: Tom Rini <trini@ti.com>
* mtd: nand: do not scan BBT after scrubMasahiro Yamada2015-01-09-8/+3
| | | | | | | | | | | | | | | | | Currently, "nand scrub" runs chip->scan_bbt at the end of nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set. It violates the intention of NAND_SKIP_BBTSCAN. Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set. Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt() right after scrub. We can be lazier here because the BBT is scanned at the next call of nand_block_checkbad(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: Mark the BBT as scanned prior to calling scan_bbt againMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | | | | | | | | | | | | | Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning) broke NAND_BBT_USE_FLASH feature. Its git-log claimed that it reinstated the change as by commit fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved "chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);". It causes recursion if scan_bbt does not find a flash based BBT and tries to write one, and the attempt to erase the BBT area causes a bad block check. Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to calling scan_bbt.). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rostislav Lisovy <lisovy@merica.cz> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com>
* mtd: nand: revive "nand scrub" commandMasahiro Yamada2015-01-09-1/+1
| | | | | | | | | Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14), the "nand scrub" command has not been working. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Heiko Schocher <hs@denx.de>
* mtd: nand: omap_gpmc: fix error handlingGuido Martínez2015-01-05-1/+2
| | | | | | | | | | | | "err" was an unsigned variable, causing negative error codes to turn into positive values, which are interpreted as an amount of succesfully corrected bitflips (and thus not an error). In particular, this resulted in that if the elm reports uncorrectable errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded. Signed-off-by: Guido Martínez <guido@vanguardiasur.com.ar> Reviewed-by: Stefan Roese <sr@denx.de>
* sf: sf_params: Add S25FL164K flash identifier infoAdnan Ali2014-12-18-0/+1
| | | | | | | | Add the necessary flash entry for the Spansion S25FL164K flash. Tested on Marvell 88F6218 based design. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: sf_params: Add S25FL116K flash supportAdnan Ali2014-12-18-0/+1
| | | | | | | Added S25FL116K flash and tested on Marvell 88F6281 based system. Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* mtd/spi: Add support for SST25WF040BShengzhou Liu2014-12-18-0/+1
| | | | | | | | Add support for SST25WF040B-40I-SN flash. Tested on T1024QDS board. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* mtd: sf: Zap ramtron driverJagannadha Sutradharudu Teki2014-12-18-405/+0
| | | | | | | | | | | | | Removed ramtron driver since the EMK boards are no longer been active, and these are the only boards used this flash driver. Commit details for EMK zap: "ppc/arm: zap EMK boards" (sha1: d58a9451e7339ed4cf2b2627e534611f427fb791) Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
* sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit v1.1 at 2024-11-06 07:51:13 +0000