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* mtd: atmel_nand: pmecc: fix bug fail to correct bit error in 1024-bytes sectorWu, Josh2013-09-04-1/+2
| | | | | | | | | | | | | | | | | The PMECC use BCH algorithm to correct error. In BCH algorithm, the primitive polynomial value is GF(2^13) for 512-bytes sector size. And it is GF(2^14) for 1024-bytes sector size. This patch will choose correct degree of the remainders (13 or 14) for different sector size. Tested in AT91SAM9X5-EK with MLC nand flash. More detail can be refered to section 5.4.1 of: AT91SAM ARM-based Embedded MPU Application Note <http://www.atmel.com/Images/doc11127.pdf> Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'u-boot-atmel/master' into 'u-boot-arm/master'Albert ARIBAUD2013-09-04-10/+188
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| * ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirementWu, Josh2013-08-22-2/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. if CONFIG_SYS_NAND_ONFI_DETECTION is defined, driver will check NAND flash's ecc minimum requirement in ONFI parameter. a) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are defined. then use it. Driver will display a WARNING if the values are different from ONFI parameters. b) if CONFIG_PMECC_CAP, CONFIG_PMECC_SECTOR_SIZE are not defined, then use the value from ONFI parameters. * If ONFI ECC parameters are in ONFI extended parameter page, since we are not support it, so assume the minimum ecc requirement is 2 bits in 512 bytes. * For non-ONFI support nand flash, also assume the minimum ecc requirement is 2 bits in 512 bytes. 2. if CONFIG_SYS_NAND_ONFI_DETECTION is not defined, just use CONFIG_PMECC_CAP and CONFIG_PMECC_SECTOR_SIZE. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * mtd: atmel_nand: alloc memory instead of use static array for pmecc dataWu, Josh2013-08-22-7/+56
| | | | | | | | | | | | | | | | In this way, the pmecc corraction capbility can change in run time. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * ARM: at91: atmel_nand: pmecc driver will select the galois table by sector sizeWu, Josh2013-08-22-1/+4
| | | | | | | | | | | | | | | | | | | | Define the galois index table offset in chip head file. So user do not need to set by himself. Driver will set it correctly according to sector_size. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> [rebased on master] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | nand_util: delete a useless variableMasahiro Yamada2013-08-22-2/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | SPDX-License-Identifier: clean up license headerYork Sun2013-08-20-16/+1
| | | | | | | | | | | | | | | | | | This patch cleans up license header in these files: board/freescale/p1022ds/spl.c drivers/mmc/fsl_esdhc_spl.c drivers/mtd/spi/fsl_espi_spl.c Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc: p1022ds: add TPL for p1022ds nand bootYing Zhang2013-08-20-7/+21
| | | | | | | | | | | | | | | | TPL is introduced in the patch "NAND: TPL : introduce the TPL based on the SPL", here enable TPL for p1022ds nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | powerpc : spi flash : Support to start from eSPI with SPLYing Zhang2013-08-20-0/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces SPL to enable a loader stub that being loaded by the code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | sf: sst: Add support for SST25WF080Jagannadha Sutradharudu Teki2013-08-07-0/+6
| | | | | | | | | | | | | | Add support for SST25WF080 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | sf: Fix code cleanupsJagannadha Sutradharudu Teki2013-08-07-15/+16
| | | | | | | | | | | | | | - CHECK: Alignment should match open parenthesis - trailing whitespace Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | sf: Fix code cleanupJagannadha Sutradharudu Teki2013-08-06-5/+6
| | | | | | | | | | | | | | - line over 80 characters. - CHECK: Alignment should match open parenthesis Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | sf: stmicro: Fix code cleanupJagannadha Sutradharudu Teki2013-08-06-4/+3
| | | | | | | | | | | | | | | | - line over 80 characters - foo * bar -> foo *bar - removed unnecessary for single statement blocks. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | sf: sst: Fix code cleanupJagannadha Sutradharudu Teki2013-08-06-12/+20
| | | | | | | | | | | | | | | | - line over 80 characters - add spaces - add tabs Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | sf: eon|spansion|ramtron: Fix code cleanupJagannadha Sutradharudu Teki2013-08-06-5/+7
| | | | | | | | | | | | | | - line over 80 characters - insert the expression in same line Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flashTom Rini2013-07-26-1/+1
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| * cfi_flash: use buffer length in unmap_physmem()Kuo-Jung Su2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the flash_detect_legacy() of drivers/mtd/cfi_flash.c feed unmap_physmem() with MAP_NOCACHE as 2nd parameter, the do_spi_flash_read_write() of common/cmd_sf.c feed unmap_physmem() with the length of the mapped buffer as 2nd parameter. It's apparently a bug, and I personally think the 2nd parameter should be the length of the mapped buffer. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Albert Aribaud <albert.u.boot@aribaud.net> CC: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-974/+70
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* mtd: mxc_nand: Fix crash after MTD resyncMarek Vasut2013-07-12-6/+4
| | | | | | | | | | | | The driver triggered a BUG() in nand_base.c:3214/nand_scan_tail() because the ecc.strength was not set in NAND_ECC_HW_SYNDROME ECC mode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Benoit Thebaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashTom Rini2013-07-01-24/+27
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| * mtd/nand: docg4: fix compiler warningsMike Dunn2013-06-26-8/+7
| | | | | | | | | | | | | | Newer gcc versions warn about unused variables. This patch corrects a few of those warnings that popped up in a build for the palmtreo680 board. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
| * dfu, nand: before write a buffer to nand, erase the nand sectorsHeiko Schocher2013-06-24-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | before writing the received buffer to nand, erase the nand sectors. If not doing this, nand write fails. See for more info here: http://lists.denx.de/pipermail/u-boot/2013-June/156361.html Using the nand erase option "spread", maybe overwrite blocks on, for example another mtd partition, if the erasing range contains bad blocks. So a limit option is added to nand_erase_opts() Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * mtd: nand: fix initialization of BBT optionsDaniel Schwierzeck2013-06-18-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | commit dfe64e2c89731a3f9950d7acd8681b68df2bae03 Author: Sergey Lapin <slapin@ossfans.org> Date: Mon Jan 14 03:46:50 2013 +0000 mtd: resync with Linux-3.7.1 changed the initialization of BBT options. Fix drivers jz4740 and s3c2410 which have not been updated yet and cause compile errors. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mtd: nand/docg4: fix driver after Linux resyncMike Dunn2013-06-17-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit dfe64e2c89731a3f9950d7acd8681b68df2bae03: mtd: resync with Linux-3.7.1 broke the docg4 driver. Specifically: - some of the prototypes of the ecc methods changed - the NAND_NO_AUTOINCR flag was removed - the ecc.strength element was added. This patch fixes these. Tested on the docg4 on my palmtre680 board. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
* | mtd: cfi_flash: Use ARRAY_SIZE at appropriate placesAxel Lin2013-06-26-4/+3
| | | | | | | | Signed-off-by: Axel Lin <axel.lin@ingics.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-06-24-135/+341
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| * | sf: Warn to use BAR for > 16MiB flashesJagannadha Sutradharudu Teki2013-06-23-0/+6
| | | | | | | | | | | | | | | | | | Warning for > 16MiB flashes to #define CONFIG_SPI_FLASH_BAR Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add debug messages on spi_flash_read_commonJagannadha Sutradharudu Teki2013-06-23-1/+11
| | | | | | | | | | | | | | | | | | | | | - Added debug's on spi_flash_read_common() - Added space Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Place the sf calls in proper orderJagannadha Sutradharudu Teki2013-06-23-92/+92
| | | | | | | | | | | | | | | | | | Placed the sf calls in proper order - erase/write/read Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Unify spi_flash write codeJagannadha Sutradharudu Teki2013-06-23-67/+63
| | | | | | | | | | | | | | | | | | | | | Move common flash write code into spi_flash_write_common(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | sf: Add flag status register polling supportJagannadha Sutradharudu Teki2013-06-23-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Flag status register polling is required for micron 512Mb flash devices onwards, for performing erase/program operations. Like polling for WIP(Write-In-Progress) bit in read status register, spi_flash_cmd_wait_ready will poll for PEC(Program-Erase-Control) bit in flag status register. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Remove spi_flash_cmd_poll_bit()Jagannadha Sutradharudu Teki2013-06-23-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no other call other than spi_flash_cmd_wait_ready(), hence removed spi_flash_cmd_poll_bit and use the poll status code spi_flash_cmd_wait_ready() itself. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: spansion: Add support for S25FL512S_64KJagannadha Sutradharudu Teki2013-06-23-0/+7
| | | | | | | | | | | | | | | | | | Add support for Spansion S25FL512S_64K SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: stmicro: Add support for N25Q1024AJagannadha Sutradharudu Teki2013-06-23-0/+6
| | | | | | | | | | | | | | | | | | Add support for Numonyx N25Q1024A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: stmicro: Add support for N25Q1024Jagannadha Sutradharudu Teki2013-06-23-0/+6
| | | | | | | | | | | | | | | | | | Add support for Numonyx N25Q1024 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: stmicro: Add support for N25Q512AJagannadha Sutradharudu Teki2013-06-23-0/+6
| | | | | | | | | | | | | | | | | | Add support for Numonyx N25Q512A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: stmicro: Add support for N25Q512Jagannadha Sutradharudu Teki2013-06-23-0/+6
| | | | | | | | | | | | | | | | | | Add support for Numonyx N25Q512 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Use spi_flash_addr() in write callJagannadha Sutradharudu Teki2013-06-23-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | Use the existing spi_flash_addr() for 3-byte addressing cmd filling in write call. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Add bank addr code in CONFIG_SPI_FLASH_BARJagannadha Sutradharudu Teki2013-06-23-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defined bank addr code on CONFIG_SPI_FLASH_BAR macro, to reduce the size for existing boards which has < 16Mbytes SPI flashes. It's upto user which has provision to use the bank addr code for flashes which has > 16Mbytes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Update sf read to support all sizes of flashesJagannadha Sutradharudu Teki2013-06-23-3/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updated the spi_flash read func to support all sizes of flashes using bank reg addr facility. The same support has been added in below patch for erase/write spi_flash functions: "sf: Support all sizes of flashes using bank addr reg facility" (sha1: c956f600cbb0943d0afe1004cdb503f4fcd8f415) With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes. sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Update sf to support all sizes of flashesJagannadha Sutradharudu Teki2013-06-23-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Read flash bank addr register at probe timeJagannadha Sutradharudu Teki2013-06-23-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read the flash bank addr register to get the state of bank in a perticular flash. and also bank write happens only when there is a change in bank selection from user. bank read only valid for flashes which has > 16Mbytes those are opearted in 3-byte addr mode, each bank occupies 16Mytes. Suppose if the flash has 64Mbytes size consists of 4 banks like bank0, bank1, bank2 and bank3. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: Discover the bank addr commandsJagannadha Sutradharudu Teki2013-06-23-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bank/Extended addr commands are specific to particular flash vendor so discover them based on the idocode0. Assign the discovered bank commands to spi_flash members so-that the bank read/write will use their specific operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: Add bank address register writing supportJagannadha Sutradharudu Teki2013-06-23-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support to program a flash bank address register. extended/bank address register contains an information to access the 4th byte addressing in 3-byte address mode. reff' the spec for more details about bank addr register in Page-63, Table 8.16 http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | sf: winbond: Add support for W25QXXXFVJagannadha Sutradharudu Teki2013-06-22-6/+6
| | | | | | | | | | | | | | | | | | Add support for Winbond W25QXXXFV SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: winbond: Add support for W25Q16DWJagannadha Sutradharudu Teki2013-06-22-0/+5
| | | | | | | | | | | | | | | | | | Add support for Winbond W25Q16DW SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: winbond: Add support for W25Q128FWJagannadha Sutradharudu Teki2013-06-22-0/+5
| | | | | | | | | | | | | | | | | | Add support for Winbond W25Q128FW SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: winbond: Update the names for W25Q 0x40XX ID's flash partsJagannadha Sutradharudu Teki2013-06-22-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use the exact names for W25Q 0x40XX ID's flash parts, as the same sizes of flashes comes with different ID's. so-that the distinguishes becomes easy with this change. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | sf: spansion: Correct name of S25FL128S 64K Sector partJagannadha Sutradharudu Teki2013-06-22-1/+1
| |/ | | | | | | | | | | | | | | | | Corrected the name of S25FL128S 64K sector part SPI flash, S25FL128S supported has been added in below commit "sf: spansion: Add support for S25FL128S" (sha1: 1bfb9f156aa66cca6bb9c773867a1f02a84b14be) Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-22-0/+86
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