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* nand: Fix some more NULL name testsScott Wood2016-09-01-1/+1
| | | | | | | | | | | Now that nand_info[] is an array of pointers we need to test the pointer itself rather than using name as a proxy for NULLness. Fixes: b616d9b0a708eb9 ("nand: Embed mtd_info in struct nand_chip") Signed-off-by: Scott Wood <oss@buserror.net> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Tony Lindgren <tony@atomide.com>
* mtd: nand: pxa3xx: use nand_set_controller_dataChris Packham2016-09-01-0/+1
| | | | | | | | | In commit 17cb4b8f327e ("mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_data") the assignment of mtd->priv was removed but was not replaced. This adds the required nand_set_controller_data() call. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* sf: sf_params: Add AT25DF321 flash supportWenyou Yang2016-07-30-1/+2
| | | | | | | | Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: Add support for N25Q016AMoritz Fischer2016-07-30-0/+1
| | | | | | | | This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* mtd: nand: fix bug writing 1 byte less than page sizeHector Palacios2016-07-24-1/+1
| | | | | | | | | | | | | | | | | | nand_do_write_ops() determines if it is writing a partial page with the formula: part_pagewr = (column || writelen < (mtd->writesize - 1)) When 'writelen' is exactly 1 byte less than the NAND page size the formula equates to zero, so the code doesn't process it as a partial write, although it should. As a consequence the function remains in the while(1) loop with 'writelen' becoming 0xffffffff and iterating until the watchdog timeout triggers. To reproduce the issue on a NAND with 2K page (0x800): => nand erase.part <partition> => nand write $loadaddr <partition> 7ff Signed-off-by: Hector Palacios <hector.palacios@digi.com>
* mtd: nand: Add a full-id entry for the H27QCG8T2E5R‐BCF NANDBoris Brezillon2016-07-24-0/+4
| | | | | | | Add a full-id entry for the H27QCG8T2E5R‐BCF NAND. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Add the sunxi NAND controller driverBoris Brezillon2016-07-24-3/+1851
| | | | | | | | | | | We already have an SPL driver for the sunxi NAND controller, now add the normal/standard one. The source has been copied from Linux 4.6 with a few changes to make it work in u-boot. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: add common DT init codeBrian Norris2016-07-24-0/+70
| | | | | | | | | | | | | | | | | These are already-documented common bindings for NAND chips. Let's handle them in nand_base. If NAND controller drivers need to act on this data before bringing up the NAND chip (e.g., fill out ECC callback functions, change HW modes, etc.), then they can do so between calling nand_scan_ident() and nand_scan_tail(). The original commit has been slightly reworked to use the fdtdec_xxx() helpers (instead of the of_xxxx() ones). Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* mtd: OneNAND: initialize mtd->writebufsize to let UBI workLadislav Michl2016-07-22-0/+1
| | | | | | | io_init checks this value and fails with "bad write buffer size 0 for 2048 min. I/O unit" Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* mtd: OneNAND: allow board init function failLadislav Michl2016-07-22-15/+15
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* mtd: OneNAND: add timeout to wait ready loopsLadislav Michl2016-07-22-11/+19
| | | | | | | | Add timeout to onenand_wait ready loop as it hangs here indefinitely when chip not present. Once there, do the same for onenand_bbt_wait as well (note: recent Linux driver code does the same) Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-1/+2
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* spl: Lightweight UBI and UBI fastmap supportThomas Gleixner2016-07-22-0/+1169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting a payload out of NAND FLASH from the SPL is a crux today, as it requires hard partioned FLASH. Not a brilliant idea with the reliability of todays NAND FLASH chips. The upstream UBI + UBI fastmap implementation which is about to brought to u-boot is too heavy weight for SPLs as it provides way more functionality than needed for a SPL and does not even fit into the restricted SPL areas which are loaded from the SoC boot ROM. So this provides a fast and lightweight implementation of UBI scanning and UBI fastmap attach. The scan and logical to physical block mapping code is developed from scratch, while the fastmap implementation is lifted from the linux kernel source and stripped down to fit the SPL needs. The text foot print on the board which I used for development is: 6854 0 0 6854 1abd drivers/mtd/ubispl/built-in.o Attaching a NAND chip with 4096 physical eraseblocks (4 blocks are reserved for the SPL) takes: In full scan mode: 1172ms In fastmap mode: 95ms The code requires quite some storage. The largest and unknown part of it is the number of fastmap blocks to read. Therefor the data structure is not put into the BSS. The code requires a pointer to free memory handed in which is initialized by the UBI attach code itself. See doc/README.ubispl for further information on how to use it. This shares the ubi-media.h and crc32 implementation of drivers/mtd/ubi There is no way to share the fastmap code, as UBISPL only utilizes the slightly modified functions ubi_attach_fastmap() and ubi_scan_fastmap() from the original kernel ubi fastmap implementation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* onenand_spl_simple: Add a simple OneNAND read functionLadislav Michl2016-07-22-0/+48
| | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* nand_spl_simple: Add a simple NAND read functionThomas Gleixner2016-07-22-0/+62
| | | | | | | | | | | To support UBI in SPL we need a simple NAND read function. Add one to nand_spl_simple and keep it as simple as it goes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Acked-by: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+24
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* mtd: cfi_flash: fix polling for bit XSR.7 on Intel chipsDaniel Schwierzeck2016-07-20-1/+1
| | | | | | | | | | | | | | | | | | flash_full_status_check() checks bit XSR.7 on Intel chips. This should be done by only checking bit 7 and not by comparing the whole status byte or word with 0x80. This fixes the non-working block erase in the pflash emulation of Qemu when used with the MIPS Malta board. MIPS Malta uses x32 mode to access the pflash device. In x32 mode Qemu mirrors the lower 16 bits of the status word into the upper 16 bits. Thus the CFI driver gets a status word of 0x8080 in x32 mode. If flash_full_status_check() uses flash_isequal(), then it polls for XSR.7 by comparing 0x8080 with 0x80 which never becomes true. Reported-by: Alon Bar-Lev <alon.barlev@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-2/+2
| | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* sunxi: Support booting from SPI flashSiarhei Siamashka2016-07-15-0/+296
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner devices support SPI flash as one of the possible bootable media type. The SPI flash chip needs to be connected to SPI0 pins (port C) to make this work. More information is available at: https://linux-sunxi.org/Bootable_SPI_flash This patch adds the initial support for booting from SPI flash. The existing SPI frameworks are not used in order to reduce the SPL code size. Right now the SPL size grows by ~370 bytes when CONFIG_SPL_SPI_SUNXI option is enabled. While there are no popular Allwinner devices with SPI flash at the moment, testing can be done using a SPI flash module (it can be bought for ~2$ on ebay) and jumper wires with the boards, which expose relevant pins on the expansion header. The SPI flash chips themselves are very cheap (some prices are even listed as low as 4 cents) and should not cost much if somebody decides to design a development board with an SPI flash chip soldered on the PCB. Another nice feature of the SPI flash is that it can be safely accessed in a device-independent way (since we know that the boot ROM is already probing these pins during the boot time). And if, for example, Olimex boards opted to use SPI flash instead of EEPROM, then they would have been able to have U-Boot installed in the SPI flash now and boot the rest of the system from the SATA hard drive. Hopefully we may see new interesting Allwinner based development boards in the future, now that the software support for the SPI flash is in a better shape :-) Testing can be done by enabling the CONFIG_SPL_SPI_SUNXI option in a board defconfig, then building U-Boot and finally flashing the resulting u-boot-sunxi-with-spl.bin binary over USB OTG with a help of the sunxi-fel tool: sunxi-fel spiflash-write 0 u-boot-sunxi-with-spl.bin The device needs to be switched into FEL (USB recovery) mode first. The most suitable boards for testing are Orange Pi PC and Pine64. Because these boards are cheap, have no built-in NAND/eMMC and expose SPI0 pins on the Raspberry Pi compatible expansion header. The A13-OLinuXino-Micro board also can be used. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: nand: Drop a blank line in nand_wait()Andre Renaud2016-06-24-1/+0
| | | | | | | This empty line should not be there. Remove it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-06-20-180/+333
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| * mtd: nand: Patch remaining places where nand_to_mtd() should be usedBoris Brezillon2016-06-19-5/+5
| | | | | | | | | | | | | | Some drivers are still directly accessing the chip->mtd field. Patch them to use nand_to_mtd() instead. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * nand: nand torture: follow sync with linux v4.6Max Krummenacher2016-06-19-1/+1
| | | | | | | | | | | | follow parameter name change (nand to mtd) to fix compiler error. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * spl: nand: sunxi: add support for NAND config auto-detectionBoris Brezillon2016-06-19-58/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND chips are supposed to expose their capabilities through advanced mechanisms like READID, ONFI or JEDEC parameter tables. While those methods are appropriate for the bootloader itself, it's way to complicated and takes too much space to fit in the SPL. Replace those mechanisms by a dumb 'trial and error' mechanism. With this new approach we can get rid of the fixed config list that was used in the sunxi NAND SPL driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: split 'load page' and 'read page' logicBoris Brezillon2016-06-19-71/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the 'load page' and 'read page' logic in 2 different functions so we can later load the page and test different ECC configs without the penalty of reloading the same page in the NAND cache. We also move common setup to a dedicated function (nand_apply_config()) to avoid rewriting the same values in NFC registers each time we read a page. These new functions are passed a pointer to an nfc_config struct to limit the number of parameters. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: rework status polling loopBoris Brezillon2016-06-19-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | check_value_xxx() helpers are using a 1ms delay between each test, which can be quite long for some operations (like a page read on an SLC NAND). Since we don't have anything to do but to poll this register, reduce the delay between each test to 1us. While we're at it, rename the max_number_of_retries parameters and the MAX_RETRIES macro into timeout_us and DEFAULT_TIMEOUT_US to reflect that we're actually waiting a given amount of time and not only a number of retries. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: stop guessing the redundant u-boot offsetBoris Brezillon2016-06-19-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND value instead of trying to guess where the redundant u-boot image is based on simple (and most of the time erroneous) heuristics. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> # Conflicts: # drivers/mtd/nand/sunxi_nand_spl.c
| * spl: nand: support redundant u-boot imageBoris Brezillon2016-06-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On modern NAND it's more than recommended to have a backup copy of the u-boot binary to recover from corruption: bitflips are quite common on MLC NANDs, and the read-disturbance will corrupt your u-boot partitition more quickly than what you would see on an SLC NAND. Add an extra Kconfig option to specify the offset of the redundant u-boot image. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com> [scottwood: added ifdef to fix build break] Signed-off-by: Scott Wood <oss@buserror.net>
| * spl: nand: rework SYS_NAND_U_BOOT_OFFS Kconfig option dependencyBoris Brezillon2016-06-19-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | The SYS_NAND_U_BOOT_OFFS is quite generic, but the Kconfig entry is forced to explicitly depend on platforms that are not already defining it in their include/configs/<board>.h header. Add the SYS_NAND_U_BOOT_LOCATIONS option, make the SYS_NAND_U_BOOT_OFFS depends on it, remove the dependency on NAND_SUNXI and make it dependent on SPL selection. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * spl: nand: sunxi: remove support for so-called 'syndrome' modeBoris Brezillon2016-06-19-42/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sunxi SPL NAND controller driver supports use 'BootROM'-like configs, that is, configs where the ECC bytes and real data are interleaved in the page instead of putting ECC bytes in the OOB area. Doing that has several drawbacks: - since you're interleaving data and ECC bytes you can't use the whole page otherwise you might override the bad block marker with non-FF bytes. - to solve the bad block marker problem, the ROM code supports partially using the page, but this introduces a huge penalty both in term of read speed and NAND memory usage. While this is fine for rather small binaries(like the SPL one which is at maximum 24KB large), it becomes non-negligible for the bootloader image (several hundred of KB). - auto-detection of the page size is not reliable (this is in my opinion the biggest problem). If you get the page size wrong, you'll end up reading data at a different offset than what was specified by the caller and the reading may succeed (if valid data were written at this address). For all those reasons I think it's wiser to completely remove support for 'syndrome' configs. If we ever need to support it again, then I'd recommend specifying all the config parameters through Kconfig options. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-13-2/+3
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| * | at91: nand: Set up the ECC strength correctlyAndre Renaud2016-06-12-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This needs to be set to avoid a fatal error when ECC is used. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | at91: Correct NAND ECC register accessAndre Renaud2016-06-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This uses the wrote base register value. Fix it. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-1/+1
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| * | mtd: nand: mxs: use simpler runtime cpu dection macrosPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Scott Wood <oss@buserror.net>
* | | mtd: nand: omap: allow to switch to BCH16Heiko Schocher2016-06-09-0/+4
| | | | | | | | | | | | | | | | | | | | | support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | nand: add nand mtd concat supportHeiko Schocher2016-06-09-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | add for nand devices mtd concat support. Generic MTD concat support is already ported to mainline, and used in the cfi_mtd driver. This patch adds it similiar for nand devices. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-06-04-2247/+876
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| * | nand: fix nand torture to use changed mtd apiMax Krummenacher2016-06-03-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mtd subsystem deprecated and renamed the direct use of the mtd_info struct's functionpointers. Instead the corresponding mtd_xxx function should be used. See also: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=3c3c10bba1e4ccb75b41442e45c1a072f6cded19 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| * | mtd: nand: Sync with Linux v4.6Scott Wood2016-06-03-171/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updates the NAND code to match Linux v4.6. The previous sync was from Linux v4.1 in commit d3963721d93fafa. Note that none of the individual NAND drivers tracked Linux closely enough to be synced themselves, other than manually applying a few cross-tree changes. Signed-off-by: Scott Wood <oss@buserror.net> Tested-by: Heiko Schocher <hs@denx.de>
| * | mtd: nand: Add page argument to write_page() etc.Scott Wood2016-06-03-46/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change is part of the Linux 4.6 sync. It is being done before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Add+use mtd_to/from_nand and nand_get/set_controller_dataScott Wood2016-06-03-307/+298
| | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
| * | nand: Embed mtd_info in struct nand_chipScott Wood2016-06-03-165/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_info[] is now an array of pointers, with the actual mtd_info instance embedded in struct nand_chip. This is in preparation for syncing the NAND code with Linux 4.6, which makes the same change to struct nand_chip. It's in a separate commit due to the large amount of changes required to accommodate the change to nand_info[]. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Remove nand_info_t typedefScott Wood2016-06-03-90/+90
| | | | | | | | | | | | | | | | | | | | | This typedef serves no purpose other than causing confusion with struct nand_chip. Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: Remove docg4 driver and palmtreo680 flashing toolScott Wood2016-06-03-1251/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ad4f54ea86b ("arm: Remove palmtreo680 board") removed the only user of the docg4 driver and the palmtreo680 image flashing tool. This patch removes them. Signed-off-by: Scott Wood <oss@buserror.net> Cc: Mike Dunn <mikedunn@newsguy.com> Cc: Simon Glass <sjg@chromium.org>
| * | mtd: nand: Remove jz4740 driverMarek Vasut2016-06-03-259/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is not used by anyone, remove it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Scott Wood <oss@buserror.net> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Scott Wood <oss@buserror.net>
| * | mtd: nand: arasan_nfc: Correct nand ecc initializationSiva Durga Prasad Paladugu2016-06-03-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the nand ecc initialization code This fixes the issue of incorrect nand ecc init if no device is found in ecc_matrix then it endsup ecc init with junk initialization instead of the most suited one. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
* | | driver: mtd: spi: Adding support for QSPI flashPrabhakar Kushwaha2016-06-03-2/+4
|/ / | | | | | | | | | | | | | | | | | | | | Serial number, vendor id and page size are added for QSPI flash common on both LS1012AQDS and LS1012ARDB i.e. S25FS512SDSMFI011. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mtd: nand: am335x: spl: Fix copying of imageLokesh Vutla2016-05-27-1/+14
| | | | | | | | | | | | | | | | | | When offset is not aligned to page address, it is possible that extra offset will be read from nand. Adjust the image such that first byte of the image is at load address after the first page is read. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | spl: Support loading a FIT from SPILokesh Vutla2016-05-27-5/+32
| | | | | | | | | | | | | | | | Detect a FIT when loading from SPI and handle it using the new FIT SPL support. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-11-07 09:39:51 +0000