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* tegra: nand: disable subpage writesMarcel Ziswiler2015-08-13-0/+3
| | | | | | | | Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mtd/nand/tegra: alignment workaroundMarcel Ziswiler2015-08-13-51/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: fix read_byte required for proper onfi detectionMarcel Ziswiler2015-08-13-31/+7
| | | | | | | | | | | | | | | | | | Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* nand: lpc32xx: add SLC NAND controller supportVladimir Zapolskiy2015-08-12-0/+177
| | | | | | | | | | | | | | | | | | | | | The change adds support of LPC32xx SLC NAND controller. LPC32xx SoC has two different mutually exclusive NAND controllers to communicate with single and multiple layer chips. This simple driver allows to specify NAND chip timings and defines custom read_buf()/write_buf() operations, because access to 8-bit data register must be 32-bit aligned. Support of hardware ECC calculation is not implemented (data correction is always done by software), since it requires a working DMA engine. The driver can be included to an SPL image. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* spl: nand: simple: replace readb() with chip specific read_buf()Vladimir Zapolskiy2015-08-12-2/+5
| | | | | | | | | | | | | | | Some NAND controllers define custom functions to read data out, respect this in order to correctly support bad block handling in simple SPL NAND framework. NAND controller specific read_buf() is used even to read 1 byte in case of connected 8-bit NAND device, it turns out that read_byte() may become outdated. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Tom Rini <trini@konsulko.com> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
* nand, atmel: remove udelay in spl_nand_erase_one()Heiko Schocher2015-08-12-2/+0
| | | | | | | | remove unneeded udelay() in this function, as we use the dev_ready pin. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* sunxi: nand: Add board configuration optionsPiotr Zierhoffer2015-08-08-0/+40
| | | | | | | | | | | | | | | When SPL_NAND_SUNXI option is selected in config, set some configuration options for sunxi NAND. This commit also introduces the configurable options in Kconfig. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: nand: Add basic sunxi NAND driver for SPL with DMA supportPiotr Zierhoffer2015-08-08-0/+354
| | | | | | | | | | | | | This driver adds NAND support to SPL. It was tested on Allwinner A20. Signed-off-by: Peter Gielda <pgielda@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Karol Gugala <kgugala@antmicro.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sf: kconfig: add kconfig options for spi flashesNikita Kiryanov2015-08-02-0/+44
| | | | | | | | | | Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig. Cc: Jagan Teki <jteki@openedev.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada2015-07-10-2/+3
| | | | | | | | | | | | | | | | | | | | | | Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* sf: Kconfig: Add SPI_FLASH_BAR entryJagan Teki2015-07-01-0/+8
| | | | | | Added SPI_FLASH_BAR entry on Kconfig with help description Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Kconfig: Add SPI_FLASH_DATAFLASH entryJagan Teki2015-07-01-10/+15
| | | | | | | | | | | Added SPI_FLASH_DATAFLASH entry on Kconfig with help description. data flash driver comes with good decription, hence moved the same on to kconfig help decription. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Haikun Wang <haikun.wang@freescale.com>
* sf: Kconfig: Add SPI_FLASH_MTD entryJagan Teki2015-07-01-0/+12
| | | | | | | | Added SPI_FLASH_MTD entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* sf: Kconfig: Update SPI_FLASH entryJagan Teki2015-07-01-9/+9
| | | | | | | Updated SPI_FLASH entry on Kconfig with depends on and along with config help description. Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: Add Kconfig menu entryJagan Teki2015-07-01-0/+4
| | | | | | Added Kconfig menu ... endmenu enties for spi flash suppor Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: dataflash: Rename to CONFIG_SPI_FLASH_DATAFLASHJagan Teki2015-07-01-1/+1
| | | | | | | Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH as it follows the naming convention same as remaining configs. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi/sf: Minor cleanupsJagan Teki2015-07-01-9/+9
| | | | | | | - Adjust tab spaces - Add comments Signed-off-by: Jagan Teki <jteki@openedev.com>
* sf: update sst25wf040b flash paramsHaikun Wang2015-06-30-1/+1
| | | | | | | | | sst25wf040b doesn't support Auto Address Increment Programming command. Remove SST_WR flag. Signed-off-by: Haikun Wang <B53464@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* mtd, nand: Move common functions from cmd_nand.c to common placeHeiko Schocher2015-06-30-2/+101
| | | | | | | | | | | | | | Move common functions from cmd_nand.c (for calculating offset and size from cmdline paramter) to common place, so they could used from other commands which use mtd partitions. For onenand the arg_off_size() is left in common/cmd_onenand.c. It should use now the common arg_off() function, but as I could not test onenand I let it there ... Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* mtd, spi: Add MTD layer driverDaniel Schwierzeck2015-06-30-5/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MTD layer driver for spi, original patch from: http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced Changes from Heiko Schocher against this patch: - Remove compile error if not defining CONFIG_SPI_FLASH_MTD: LD drivers/mtd/spi/built-in.o drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister': /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister' drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister': /home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister' drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1 make: *** [drivers/mtd/spi] Fehler 2 - Add a README entry. - Add correct writebufsize, to fit with Linux v3.14 MTD, UBI/UBIFS sync. Note (From Jagan): For testing raw mtd parition erase/read/write operations using cmd_sf, sf_mtd should be required to register the spi flash device to MTD layer but the sf_mtd_info ops were not required until and unless if we use any flash filesystem layer say for example UBI. Due to this the foot-print got increased ~290bytes in non-UBI case here that should be acceptible. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Heiko Schocher <hs@denx.de> Tested-by: Jagannadh Teki <jteki@openedev.com> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* dm: sf: Add Atmel DataFlash spi flash driverHaikun Wang2015-06-30-0/+712
| | | | | | | | | | | | | | | | | | | | | | | | | | Atmel DataFlash chips have commands different from common spi flash commands. Atmel DataFlash also have special page-size. This driver add support for accessing Atmel DataFlash. It is based on the Driver Model. Example: => sf probe 1:0 SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d => sf erase 0 42000 SF: 270336 bytes @ 0x0 Erased: OK => mw.l 82000000 45444342 20000 => sf write 82000000 0 42000 SF: 270336 bytes @ 0x0 Written: OK => sf read 83000000 0 42000 SF: 270336 bytes @ 0x0 Read: OK => cmp.b 82000000 83000000 42000 Total of 270336 byte(s) were the same Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Tested-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chakra Divi <cdivi@openedev.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal ↵Ian Campbell2015-06-28-274/+0
| | | | | | | | | | | | | | NAND memory" This reverts commit f76eba38b3eda905ff3bdc18dd1240d3dcbc6e5a. This patch did not have a full and proper copyright/S-o-b chain. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Conflicts: include/configs/sun6i.h include/configs/sun8i.h
* mtd: spi: Add the SPI_FLASH config to KconfigJoe Hershberger2015-06-25-0/+9
| | | | | | | This config needs to be available in the Kconfig to allow it to be removed from arch defaults. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* mtd: OMAP: Enable GPMC prefetch mode for 16 bit accessJeroen Hofstee2015-06-18-10/+18
| | | | | | | | | | | | commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled prefetch mode for 8 bit nand access, this adds 16 bit as well. Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Daniel Mack <zonque@gmail.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELMJeroen Hofstee2015-06-18-109/+109
| | | | | | | | | | | | | The prefech mode is a feature of the gpmc, not the ELM. An am3517 does not have an elm, but can do prefeches, so move the code out of the CONFIG_NAND_OMAP_ELM ifdef. Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@konsulko.com> Cc: Daniel Mack <zonque@gmail.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: Tom Rini <trini@konsulko.com>
* sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memoryDaniel Kochmański2015-05-29-0/+274
| | | | | | | | | | | This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mtd: vf610_nfc: enable ONFI detectionStefan Agner2015-05-24-18/+49
| | | | | | | | | | This changes enable ONFI detection. The Read ID command now allows one address byte which is needed for ONFI detection. To read the ONFI parameter page, the NAND_CMD_PARAM need to be supported. The CMD code enables one command and one address byte along with reading data from flash using R/B#, as specified by ONFI. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: add 32-error correction option for HW ECCStefan Agner2015-05-24-5/+50
| | | | | | | | | Add option to choose between current 24-error correction and 32-error correction through Kconfig. 32-error correction allow to use NAND chips which require up to 8-bit error correction per 512 byte (when using 2K pages). Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: add Freescale NFC controller configs to KconfigStefan Agner2015-05-24-0/+30
| | | | | | | | | | | This commit allows users to enable/disable the Freescale NFC controller found in systems like Vybrid (VF610), MPC5125, MCF54418 or Kinetis K70 via Kconfig with more detailed help docs. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefano Babic <sbabic@denx.de> [scottwood: updated vf610twr_nand_defconfig] Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: vf610_nfc: use in-band bad block tableStefan Agner2015-05-24-27/+2
| | | | | | | | | Use in-band bad block table (NAND_BBT_NO_OOB) which allows to use the full OOB for hardare ECC purposes. Since there is no ECC correction on the OOB it is also safer to use in-band area to store the bad block table marker. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: implement OOB only readStefan Agner2015-05-24-59/+40
| | | | | | | | | | | | | | | | | | Implement read of OOB area only. When using column and sector size properties, only parts of the page can be read. However, this works only when hardware ECC is disabled, otherwise the ECC engine would ruin the data in the buffer. To allow OOB only reads, three points had to be addressed: - Set ECC mode per command. - Handle NAND_CMD_READOOB seperate. Make sure column and sector size is correctly set up, while disabling ECC. - Now, the OOB data end up at the beginning of the buffer. Remove the special handling of OOB (spareonly). Especially bad block scans benefit from this change. On a 512MiB SLC NAND device, the bad block scan took 1.5s less than before. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: allow bitflips in an empty pageStefan Agner2015-05-24-1/+1
| | | | | | | Allow bit flips in a empty page up to half of the recoverable bits (strength / 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: remove read on SEQINStefan Agner2015-05-24-6/+8
| | | | | | | | | | | Since we do not support sub-page writes anyway, reading the page back to the controller on SEQIN command is not required. Remove the page read on SEQIN. However, the column/page values relevant to the SEQIN command, hence set the column/row address on SEQIN command. Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: vf610_nfc: remove caching of page in bufferStefan Agner2015-05-24-10/+1
| | | | | | | | | | To improve performance we remember the current page in the buffer and avoid reading it twice. This implicit page cache increases complexity while does not increase performance in real world cases. This patch removes that feature. Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Stefan Agner <stefan@agner.ch>
* mtd: nand: mxs: Replace magic number for bits per ECC level with macroJörg Krause2015-05-24-3/+4
| | | | | Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Reviewed-by: Marek Vasut <marex@denx.de>
* mtd:mxs:nand calculate ecc strength dynamicallyPeng Fan2015-05-24-18/+12
| | | | | | | | | | Calculate ecc strength according oobsize, but not hardcoded which is not aligned with kernel driver Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <b37916@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
* nand/elbc: Memory leak fixRaghav Dogra2015-05-22-0/+1
| | | | | | | | | Freeing allocated memory to priv before returning from the function Signed-off-by: Raghav Dogra <raghav@freescale.com> [scottwood: removed unnecessary cast] Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand: fix buffer alignment in new verification featureStephen Warren2015-05-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | On systems with caches enabled, NAND I/O may need to flush/invalidate the cache during read/write operations. For this to work correctly, all buffers must be cache-aligned. Fix nand_verify*() to allocate aligned buffers. This prevents cache alignment warnings from being spewed when using U-Boot to write an updated version of itself to flash on NVIDIA Tegra Seaboard (after perturbation of stack/data layout in current u-boot-dm/next branch). I have validatd (executed) nand_verify(), but I don't think I've executed nand_verify_page_oob(); testing of that would be useful. Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Fixes: 59b5a2ad83df ("nand: Add verification functions") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Scott Wood <scottwood@freescale.com>
* sandbox: spi: Add newline to printf() in sandbox_sf_probeSimon Glass2015-05-14-1/+1
| | | | | | | | This printf() should have a newline at the end. Add it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* dm: sf: Update default name of spi flash in structure udeviceHaikun.Wang@freescale.com2015-05-06-2/+2
| | | | | | | Default name of spi flash like this "0:0", update it to "spi_flash@0:0". Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-04-28-42/+46
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| * sf: Fix to compute proper sector_sizeJagannadha Sutradharudu Teki2015-04-28-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upto now flash sector_size is assigned from params which isn't necessarily a sector size from vendor, so based on the SECT_* flags from flash_params the erase_size will compute and it will become the sector_size finally. Bug report (from Bin Meng): => sf probe SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB, total 2 MiB, mapped at ffe00000 => sf erase 0 +100 SF: 65536 bytes @ 0x0 Erased: OK Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reported-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: sf: Make SST flash write op work againBin Meng2015-04-28-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | With SPI flash moving to driver model, commit fbb0991 "dm: Convert spi_flash_probe() and 'sf probe' to use driver model" ignored the SST flash-specific write op (byte program & word program), which actually broke the SST flash from wroking. This commit makes SST flash work again under driver model, by adding SST flash-specific handling in the spi_flash_std_write(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * dm: sf: Save flash flags to struct spi_flashBin Meng2015-04-28-0/+3
| | | | | | | | | | | | | | | | Add a new member 'flags' in struct spi_flash to store the flash flags during spi_flash_validate_params(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * Revert "spi: add config option to enable the WP pin function on st micron ↵Jagannadha Sutradharudu Teki2015-04-23-34/+0
| | | | | | | | | | | | | | | | | | | | | | | | flashes" This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d. Note: Even un-reverting this patch couldn't works as expected, based on the latest testing from Heiko Schocher. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Cc: Heiko Schocher <hs@denx.de>
| * mtd: spi: check return value of spi_setup_slavePeng Fan2015-04-22-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to check value of spi_setup_slave and spi_setup_slave_fdt. If their return value 'bus' is NULL, there is no need to pass it to following spi_flash_probe_tail. If 'bus' is null, the original function flow is as following: spi_flash_probe |->spi_setup_slave |->spi_probe_bus_tail |->spi_flash_probe_slave |->spi_free_slave Alougth check the pointer in spi_free_slave is ok, checking the return value of spi_setup_slave and spi_setup_slave_fdt is better. Before this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! SF: Failed to set up slave data abort pc : [<fff66dcc>] lr : [<fff7628c>] reloc pc : [<87814dcc>] lr : [<8782428c>] sp : fdf4fcf0 ip : e630396c fp : fe0d0888 r10: fffa2538 r9 : fdf4feb8 r8 : 02625a00 r7 : 00000002 r6 : fff94ec0 r5 : 00000000 r4 : 9355553c r3 : 1af0593c r2 : cb3fe030 r1 : fff94eb8 r0 : e59ff018 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... " After this fix: " => sf probe 0:2 FSL_QSPI: Not a valid cs ! Failed to initialize SPI flash at 0:2 " No data abort using this patch. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: Poll both the read status and flag statusSiva Durga Prasad Paladugu2015-04-22-7/+25
| | | | | | | | | | | | | | | | | | Poll both the Read status and Flag status registers for sucessful erase and program operations for the Micron devices with E_FSR flag set in params table. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | armv8/ls2085aqds: NAND boot supportScott Wood2015-04-23-1/+1
| | | | | | | | | | | | | | | | | | This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
* | driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-23-24/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | nand/fsl_ifc: Increase eccstat[] for IFC 2.0Scott Wood2015-04-23-2/+9
|/ | | | | | | | IFC 2.0 doubled the SRAM size, which means double the number of ECCSTAT registers. Fix the resulting array overflow. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-14 21:40:25 +0000