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* Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-1/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * mtd: nand: Check if NAND is locked tight before lock cmdsJoe Hershberger2013-02-22-1/+18
| | | | | | | | | | | | | | | | | | If the NAND is locked tight, commands such as lock and unlock will not work, but the NAND chip may not report an error. Check the lock tight status before attempting such operations so that an error status can be reported if we know the operation will not succeed. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * kmeter1_nand: allow uasge of NAND_ECC_SOFT_BCHHolger Brunck2013-02-15-0/+4
| | | | | | | | | | | | | | | | | | If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code instead of the 1-bit error correction code on the NAND device within this driver. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | SPL: ONENAND: Fix onenand_spl_load_image implementation.Enric Balletbo i Serra2013-03-08-8/+6
|/ | | | | | | | | | Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation doesn't work. This patch fixes this function changing the read loop and reading the onenand blocks from page to page. Tested with various IGEP based boards with a OneNAND from Numonyx. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* sf: stmicro: Add support for N25Q256AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q256A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q32AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q32A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q32Jagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q32 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q64AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q64A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: winbond: Add W25Q64WJagannadha Sutradharudu Teki2013-02-06-0/+5
| | | | | | | | Add support for Winbond's W25Q64W SPI flash. This device is used on xilinx zynq emulation platform. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: spansion: Correct the first byte of idcode1 for S25FL256S partJagannadha Sutradharudu Teki2013-02-06-1/+1
| | | | | | | This patch corrected the first byte of idcode1 for S25FL256S SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: add support for N25Q064Jagannadha Sutradharudu Teki2013-02-04-0/+6
| | | | | | Add support for Numonyx N25Q064 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* cfi_flash: Report Advanced Sector Protection (PPB) with flinfo cmdStefan Roese2013-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | Report the usage of the Advanced Sector Protection (PPB) to the user upon 'flinfo' command. E.g: Bank # 1: CFI conformant flash (16 x 16) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301 Advanced Sector Protection (PPB) enabled Erase timeout: 16384 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: FC000000 E FC020000 E RO FC040000 E FC060000 E FC080000 E ... Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Enable PPB protection for all AMD cmdset flash chipsStefan Roese2013-01-10-8/+5
| | | | | | | | | | | | | | | Not only Spansion supports the Persistent Protection Bits (PPB) locking. Other devices like the Micron JS28F512M29EWx also support this type of locking/unlocking. Detection of support is done in the same way as done for the Spansion chips - via the 0x49 CFI word. This patch enables this PPB protection mechanism for all AMD type (AMD commandset) chips. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Read PPB sector protection from device for AMD/Spansion chipsStefan Roese2013-01-10-0/+21
| | | | | | | | | | | | | | | | Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector protection] introduced the PPB (Persistent Protection Bit) locking for Spansion chips. But right now the sector protection status (locked vs unlocked) is set to unlocked for all sectors upon bootup. The real sector protection status is ignored. This patch now reads the current sector protection status and uses it for these AMD/Spansion flash chips. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Add manufact_match helper functionStefan Roese2013-01-10-7/+9
| | | | | | | | Consolidate manufacturer matching into the function manufact_match() and use it. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* mtd/cfi: add support for SST 4KB sector granularityAngelo Dureghello2013-01-10-1/+24
| | | | | | | | | | | | | | | | | | | Add support for SST 4KB sector granularity. Many recent SST flashes, i.e. SST39VF3201B and similar of this family are declared CFI-conformant from SST. They support CFI query, but implement 2 different sector sizes in the same memory: a 64KB sector (they call it "block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector", erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh of cfi query struct, detects a number of secotrs for the 4KB granularity (flinfo shows it). For all other aspects, they are CFI compliant, so, as Linux do, i think it's a good idea to handle these chips in the CFI driver, with a fixup to allow 4KB granularity, as should be expected, instead of 64KB. Signed-off-by: Angelo Dureghello <sysamfw@gmail.com> Signed-off-by: Stefan Rose <sr@denx.de>
* Fix SPL build for non-ARM targetsAlbert ARIBAUD2013-01-09-0/+4
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-01-08-5/+641
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| * Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-5/+641
| |\ | | | | | | | | | | | | This required manual merging drivers/mtd/nand/Makefile and adding am335x_evm support for CONFIG_SPL_NAND_DRIVERS
| | * am33xx_spl_bch: simple SPL nand loader for AM33XXIlya Yanok2012-12-10-0/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM33XX with BCH8 can't work with nand_spl_simple correctly because custom read_page implementation is required for proper syndrome generation. This simple driver mostly duplicates nand_spl_simple but has nand_read_page changed to suit our needs. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
| | * omap_gpmc: BCH8 support (ELM based)Mansoor Ahamed2012-12-10-1/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for BCH8 error correction code to omap_gpmc driver. We use GPMC to generate codes/syndromes but we need ELM to find error locations from given syndrome. Signed-off-by: Mansoor Ahamed <mansoor.ahamed@ti.com> [ilya: merge it with omap_gpmc driver, some fixes and cleanup] Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* | | driver/mtd/IFC:Wait tWB time, poll R/B before command executionPrabhakar Kushwaha2012-12-21-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | IFC_FIR_OP_CMD0 issues command for execution without checking flash readiness. It may cause problem if flash is not ready. Instead use IFC_FIR_OP_CW0 which Wait for tWB time and poll R/B to return high or time-out, before issuing command. NAND_CMD_READID command implemention does not fulfill above requirement. So update its programming. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Hemant Nautiyal <hemant.nautiyal@freescale.com>
* | mtd: nand: mxs: reset BCH earlier, too, to avoid NAND startup problemsWolfram Sang2012-12-11-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | It could happen (1 out of 100 times) that NAND did not start up correctly after warm rebooting, so we end up with various failures or DMA timed out due to a stalled BCH. When resetting BCH together with GPMI, the issue could not be observed anymore (after 10000+ reboots). We probably need the consistent state already before sending commands to NAND. This behaviour was observed in barebox and kernel, so I assume it affects U-Boot as well. I chose to keep the extra reset for BCH when changing the flash layout to be on the safe side. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marek Vasut <marex@denx.de>
* | nand: Add torture featureBenoît Thébaudeau2012-11-26-0/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a NAND Flash torture feature, which is useful as a block stress test to determine if a block is still good and reliable (or should be marked as bad), e.g. after a write error. This code is ported from mtd-utils' lib/libmtd.c. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: removed unnec. ifdef and unwrapped error strings] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | nand: Fix nand_erase_opts() offset checkBenoît Thébaudeau2012-11-26-2/+2
| | | | | | | | | | | | | | NAND Flash is erased by blocks, not by pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com>
* | nand: Clean up nand_utilBenoît Thébaudeau2012-11-26-32/+32
| | | | | | | | | | | | | | | | | | | | | | This patch cleans up nand_util.c: - Fix tabs. - Fix typos. - Remove space character before opening parenthesis in function calls. - Fix comments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com>
* | nand: Move the sub-page read support enable to a flagJoe Hershberger2012-11-26-2/+7
| | | | | | | | | | | | | | | | | | Use a flag instead of a hard-coded macro so that sub-page reads can be enabled in other cases (such as on-die ecc). This is the same as a5ff4f102937a3492bca4a9ff0c341d78813414c in Linux Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | driver/mtd:IFC NAND:Initialise internal SRAM before any writePrabhakar Kushwaha2012-11-26-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [scottwood@freescale.com: fix fsl_ifc_sram_init prototype] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | nand/fsl: add NAND_NO_SUBPAGE_WRITE to eLBC and IFC driversScott Wood2012-11-26-2/+2
| | | | | | | | | | | | These controllers can only do hardware ECC on full page transfers. Signed-off-by: Scott Wood <scottwood@freescale.com>
* | spl/nand: config symbol documentationScott Wood2012-11-26-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | Document parameters used for specifying the NAND image to be loaded. Also fix the definition of CONFIG_SPL_NAND_SIMPLE -- it's only nand_spl_simple.c, not the entire nand directory. The word "simple" is there for a reason. :-) Signed-off-by: Scott Wood <scottwood@freescale.com> --- v2: updated for makefile changes earlier in patchset
* | spl/nand: introduce CONFIG_SPL_NAND_DRIVERS, _BASE, and _ECC.Scott Wood2012-11-26-8/+22
|/ | | | | | | | | | | | | | Some small SPLs do not use nand_base.c, and a subset of those also require a special driver. Some SPLs need software ECC but others can't fit it. All existing boards that specify CONFIG_SPL_NAND_SUPPORT have these symbols added to preserve existing behavior. Signed-off-by: Scott Wood <scottwood@freescale.com> -- v2: use positive logic for including bits of NAND, rather than a MINIMAL symbol that excludes things.
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-11-05-0/+36
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| * tegra: nand: make ONFI detection workLucas Stach2012-10-29-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | Add the missing bits to the Tegra NAND driver to make ONFI detection work properly. Also add it to the Tegra default config, as it seems to be a reasonable thing to have it available on all boards that use any kind of NAND. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | drivers/mtd/nand: sparse fixesKim Phillips2012-11-04-6/+8
| | | | | | | | | | | | | | | | | | | | nand_ecc.c:82:5: warning: symbol 'nand_calculate_ecc' was not declared. Should it be static? nand_ecc.c:155:5: warning: symbol 'nand_correct_data' was not declared. Should it be static? nand_base.c:2854:1: error: directive in argument list nand_base.c:2856:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | drivers/mtd/cfi_flash.c: sparse fixesKim Phillips2012-11-04-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | cfi_flash.c:756:43: warning: Using plain integer as NULL pointer cfi_flash.c:1150:52: warning: cast to non-scalar cfi_flash.c:1433:46: warning: cast truncates bits from constant value (890089 becomes 89) cfi_flash.c:1490:61: warning: cast truncates bits from constant value (1f001f becomes 1f) cfi_flash.c:1508:61: warning: cast truncates bits from constant value (10001 becomes 1) cfi_flash.c:1738:63: warning: cast truncates bits from constant value (10001 becomes 1) cfi_flash.c:1857:6: warning: symbol '__flash_cmd_reset' was not declared. Should it be static? Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | include/linux/byteorder: import latest endian definitions from linuxKim Phillips2012-11-04-10/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | u-boot's byteorder headers did not contain endianness attributions for use with sparse, causing a lot of false positives. Import the kernel's latest definitions, and enable them by including compiler.h and types.h. They come with 'const' added for some swab functions, so fix those up, too: include/linux/byteorder/big_endian.h:46:2: warning: passing argument 1 of '__swab64p' discards 'const' qualifier from pointer target type [enabled by default] Also, note: u-boot's historic __BYTE_ORDER definition has been preserved (for the time being at least). We also remove ad-hoc barrier() definitions, since we're including compiler.h in files that hadn't in the past: macb.c:54:0: warning: "barrier" redefined [enabled by default] In addition, including compiler.h in byteorder changes the 'noinline' definition to expand to __attribute__((noinline)). This fixes arch/powerpc/lib/bootm.c: bootm.c:329:16: error: attribute '__attribute__': unknown attribute bootm.c:329:16: error: expected ')' before '__attribute__' bootm.c:329:25: error: expected identifier or '(' before ')' token powerpc sparse builds yield: include/common.h:356:22: error: marked inline, but without a definition the unknown-reason inlining without a definition is considered obsolete given it was part of the 2002 initial commit, and no arm version was 'fixed.' also fixed: ydirectenv.h:60:0: warning: "inline" redefined [enabled by default] and: Configuring for devconcenter - Board: intip, Options: DEVCONCENTER make[1]: *** [4xx_ibm_ddr2_autocalib.o] Error 1 make: *** [arch/powerpc/cpu/ppc4xx/libppc4xx.o] Error 2 powerpc-fsl-linux-size: './u-boot': No such file 4xx_ibm_ddr2_autocalib.c: In function 'DQS_autocalibration': include/asm/ppc4xx-sdram.h:1407:13: sorry, unimplemented: inlining failed in call to 'ppc4xx_ibm_ddr2_register_dump': function body not available 4xx_ibm_ddr2_autocalib.c:1243:32: sorry, unimplemented: called from here and: In file included from crc32.c:50:0: crc32table.h:4:1: warning: implicit declaration of function '___constant_swab32' [-Wimplicit-function-declaration] crc32table.h:4:1: error: initializer element is not constant crc32table.h:4:1: error: (near initialization for 'crc32table_le[0]') Signed-off-by: Kim Phillips <kim.phillips@freescale.com> [trini: Remove '#endif' in include/common.h around setenv portion] Signed-off-by: Tom Rini <trini@ti.com>
* tegra: nand: add board pinmuxLucas Stach2012-10-15-1/+0
| | | | | | | | Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Tegra20: Move some include files to arch-tegra for sharing with Tegra30Tom Warren2012-10-15-3/+2
| | | | | | | | | | | The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
* MPC85xx: remove support for TQM85xx boardsWolfgang Denk2012-10-05-5/+5
| | | | | | | | | | | | Due to grown code sizes the TQM85xx boards don't build any more with some older tool chains (like ELDK 4.2). As these boards have long reached EOL it seems a waste of effort trying to fix them. The vendor has agreed to drop support for them, too. So let's get rid of them. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: Stefan Roese <sr@denx.de>
* Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD2012-09-30-275/+158
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| * SPL: SPI: Enhance spi_spl_load to match the other load functionsTom Rini2012-09-27-11/+12
| | | | | | | | Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2012-09-21-2/+1287
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| * | mxc nand: Fix warning on !MXC_NFC_V2_1Tom Rini2012-09-18-0/+2
| | | | | | | | | | | | | | | | | | | | | In board_nand_init() we only need the 'tmp' variable if MXC_NFC_V2_1 is defined. Signed-off-by: Tom Rini <trini@ti.com>
| * | mxc nand: Homogenize IP revisions with LinuxBenoît Thébaudeau2012-09-17-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same IP revisions as in Linux in order to make the comparison more clear. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd mxc nand: Merge init functionsBenoît Thébaudeau2012-09-17-30/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge mxc_setup_config1() into board_nand_init() in order to ease the addition of i.MX5 support in the following patches. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd mxc nand: Fix ECC state after read_page_raw_syndrome()Benoît Thébaudeau2012-09-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mxc_nand_read_page_raw_syndrome() should reenable ECC upon exit. This fixes ECC errors left uncorrected after a call to this function. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mtd mxc nand: Use _mxc_nand_enable_hwecc()Benoît Thébaudeau2012-09-17-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use _mxc_nand_enable_hwecc() instead of duplicating its code. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mxc nand: Access all ecc_status_result fieldsBenoît Thébaudeau2012-09-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the NFC IP 1.1, the 32-bit ecc_status_result value comes from 2 consecutive 16-bit registers. This patch reads all the fields of this value, which makes a difference for 4-kiB NF pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mxc nand: cosmectic: Light cleanupBenoît Thébaudeau2012-09-17-6/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | mxc nand: Merge mtd and spl register definitionsBenoît Thébaudeau2012-09-17-196/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patches fixes the TODO to use same register definitions in mtd mxc_nand and nand_spl fsl nfc drivers. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
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