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* NAND: fix "raw" reads with ECC syndrome layoutsDavid Brownell2009-11-13-4/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome based page read/write routines store ECC, and possibly other "OOB" data, right after each chunk of ECC'd data. With ECC chunk size of 512 bytes and a large page (2KiB) NAND, the layout is: data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines use a traditional layout -- data OOB, disregarding the prepad and postpad values -- so when they're used with that type of ECC hardware, those calls mix up the data and OOB. Which means, in particular, that bad block tables won't be found on startup, with data corruption and related chaos ensuing. The current syndrome-based drivers in mainline all seem to use one chunk per page; presumably they haven't noticed such bugs. Fix this, by adding read/write page_raw_syndrome() routines as siblings of the existing non-raw routines; "raw" just means to bypass the ECC computations, not change data and OOB layout. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
* NAND: Don't walk past end of oobfree[]Sandeep Paulraj2009-11-13-1/+2
| | | | | | | | When computing oobavail from the list of free areas in the OOB, don't assume there will always be an unused slot at the end. This syncs up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Update check condition for nand_read_page_hwecc APISandeep Paulraj2009-11-13-1/+1
| | | | | | | | The patch updates the check condition for determining whether the ECC corrections has failed. This makes it similar to what is in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Updating comments/explanations in the NAND driverSandeep Paulraj2009-11-13-4/+8
| | | | | | | Patch updates the comments and explanations for the arguments to various functions. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Subpage shift for ecc_steps equal to 16Sandeep Paulraj2009-11-13-0/+1
| | | | | | | | | This was originally part of Thomas Gleixner's patch for adding support for 4KiB pages. This is not part of the U-Boot NAND driver so updating the driver with this to sync up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Remove commented out codeSandeep Paulraj2009-11-13-1/+0
| | | | | | Patch removes already commented out dead code Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Correct the "chip_shift" calculationSandeep Paulraj2009-11-13-1/+1
| | | | | | | | This patch updates the "chip_shift" calculation in the NAND driver. This is being done to sync up the NAND driver with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: Update to support 64 bit device sizeSandeep Paulraj2009-11-13-28/+39
| | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-133/+18
| | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
* sf: add GPL-2 license infoMike Frysinger2009-10-24-0/+2
| | | | | | | Some of the new spi flash files were missing explicit license lines. Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* Clean-up of s3c24x0 nand driverkevin.morfitt@fearnside-systems.co.uk2009-10-13-37/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patches 1/4, 2/4 and 3/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* s5pc1xx: support onenand driverMinkyu Kang2009-10-13-0/+637
| | | | | | | This patch includes the onenand driver for s5pc100 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* Conditionally perform common relocation fixupsPeter Tyser2009-10-03-0/+2
| | | | | | | | | | | Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* NAND: davinci: Fix warnings when 4-bit ECC not usedScott Wood2009-09-28-2/+1
| | | | | | | | | I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mpc512x. Micron nand flash needs a reset before a read command is issued.Paul Gibson2009-09-22-0/+1
| | | | | Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
* ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-2/+2
| | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* mxc_nand: Remove Freescale's "All Rights Reserved."Scott Wood2009-09-04-1/+1
| | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-2/+282
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRSTSandeep Paulraj2009-08-26-0/+59
| | | | | | | | | | | | | | | | | This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mxc_nand: add nand driver for MX2/MX3Ilya Yanok2009-08-26-0/+881
| | | | | | | | | Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: ADD page Parameter to all read_page/read_page_raw API'sSandeep Paulraj2009-08-26-8/+10
| | | | | | | | | | | | | | | | This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 83xx, kmeter1: added NAND supportHeiko Schocher2009-08-26-0/+136
| | | | | Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* OneNAND: Remove unused read_spareramKyungmin Park2009-08-26-3/+1
| | | | | | | Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* KB9202: Add NAND supportMatthias Kaehlcke2009-08-26-0/+151
| | | | | | | Add KB9202 NAND driver Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Support up to 7 banks for ids as specified in JEDEC JEP106ZNiklaus Giger2009-08-26-2/+80
| | | | | | | | see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driverFeng Kan2009-08-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by: Feng Kan <fkan@amcc.com> Acked-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* eeprom_m95xxx: remove unused variable iJean-Christophe PLAGNIOL-VILLARD2009-08-21-1/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* add WATCHDOG_RESET() on nand write and readGiulio Benetti2009-08-21-0/+4
| | | | | | Signed-off-by: giulio.benetti@micronovasrl.com Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* flash: Fix CFI buffer size bugJohn Schmoller2009-08-13-1/+1
| | | | | | | | | | | | Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51. The cfi_flash.c driver cast the flash buffer size to a uchar in flash_write_cfibuffer(). On some flash parts, (tested on Numonyx part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to uchar to enable buffer sizes to be larger. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Add driver for the ST M95xxx SPI EEPROMAlbin Tonnerre2009-08-09-0/+118
| | | | | | | | This chip is used in a number of boards manufactured by Calao-Systems which should be supported soon. This driver provides the necessary spi_read and spi_write functions necessary to communicate with the chip. Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
* omap3: replace all instances of gpmc config struct by one globalDirk Behme2009-08-08-17/+16
| | | | | Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* omap3: remove typedefs for configuration structsDirk Behme2009-08-08-1/+1
| | | | | Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* omap3: embedd gpmc_cs into gpmc config structMatthias Ludwig2009-08-07-15/+7
| | | | | | | | | Embedd chip select configuration into struct for gpmc config instead of having it completely separated as suggested by Wolfgang Denk on http://lists.denx.de/pipermail/u-boot/2009-May/052247.html Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
* Remove legacy NAND and disk on chip code.Scott Wood2009-07-16-1663/+0
| | | | | | | | | | | | | Legacy NAND had been scheduled for removal. Any boards that use this were already not building in the previous release due to an #error. The disk on chip code in common/cmd_doc.c relies on legacy NAND, and it has also been removed. There is newer disk on chip code in drivers/mtd/nand; someone with access to hardware and sufficient time and motivation can try to get that working, but for now disk on chip is not supported. Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand: ndfc: Remove unnecessary #ifdef'sStefan Roese2009-07-16-6/+0
| | | | | | | | | Now that the 4xx NAND driver ndfc is moved to the common NAND driver directory we don't need this #ifdef's anymore. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-16-0/+224
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nand: fixed failed reads on corrected ECC errors in nand_util.cValeriy Glushkov2009-07-16-5/+5
| | | | | | Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Paulraj, Sandeep <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Typo fix: use CONFIG_SOC_DM644X, not CONFIG_SOC_DM646.David Brownell2009-07-16-1/+1
| | | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: cfi - if defined, use MAX_FLASH_BANKS_DETECT for static declarationsKim Phillips2009-07-16-2/+9
| | | | | | | | | | | | | a.k.a cfi_mtd.c does as cfi_flash.c does. This also prevents the TQM834x build from doing a: cfi_mtd.c:36: error: variably modified 'cfi_mtd_info' at file scope cfi_mtd.c:37: error: variably modified 'cfi_mtd_names' at file scope using gcc 4.4. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-0/+83
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| * nand: Add Marvell Kirkwood NAND driverPrafulla Wadaskar2009-07-08-0/+83
| | | | | | | | | | | | | | This patch adds a NAND driver for the Marvell Kirkwood SoC's Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | issue write command to base for JEDEC flashPo-Yu Chuang2009-07-13-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For JEDEC flash, we should issue word programming command relative to base address rather than sector base address. Original source makes SST Flash fails to program sectors which are not on the 0x10000 boundaries. e.g. SST39LF040 uses addr1=0x5555 and addr2=0x2AAA, however, each sector is 0x1000 bytes. Thus, if we issue command to "sector base (0x41000) + offset(0x5555)", it sends to 0x46555 and the chip fails to recognize that address. This patch is tested with SST39LF040. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | fsl_elbc_nand: redirect the pointer of bbt pattern to RAMMingkai Hu2009-07-07-0/+4
| | | | | | | | | | | | | | | | | | | | | | The bbt descriptors contains the pointer to the bbt pattern which are statically initialized memory struct. When relocated to RAM, these pointers will continue point to NOR flash(or L2 SRAM, or other boot device). If the contents of NOR flash changed or L2 SRAM disabled, it'll hang the system. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Bug-fix in drivers mtd nand Makefilekevin.morfitt@fearnside-systems.co.uk2009-07-07-1/+1
| | | | | | | | | | | | | | | | The S3C2410 NAND driver source file is included in the makefile instead of the object file. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand: use loff_t for offsetJean-Christophe PLAGNIOL-VILLARD2009-07-07-10/+10
| | | | | | | | | | | | | | | | nand_util currently uses size_t which is arch dependent and not always a unsigned long. Now use loff_t, as does the linux mtd layer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand: new base driver for memory mapped nand devicesMike Frysinger2009-07-07-0/+54
| | | | | | | | | | | | | | | | | | The BF537-STAMP Blackfin board had a driver for working with NAND devices that are simply memory mapped. Since there is nothing Blackfin specific about this, generalize the driver a bit so that everyone can leverage it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | davinci_nand chipselect/init cleanupDavid Brownell2009-07-07-20/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)David Brownell2009-07-07-205/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | davinci_nand: cleanup I (minor)David Brownell2009-07-07-33/+22
|/ | | | | | | | | | | | | | | | | | | | | | | | Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-9/+3
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
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