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* Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips.Philippe De Muyter2010-08-18-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips. After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update" It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks. A working workaround is given, which I have applied and tested with success : Workaround: If the interval between 60h and its subsequent command can be guaranteed within 20us, Option I is recommended, otherwise Option II (involves hardware) should be selected. Option I: The table below lists the detail command sequences: Command Data bus Address bus Remarks Sequence 1 90h Block Address Read Lock Status 2 Read Block Address + 02h (2)(3) (1) 3 60h Block Address (2)(3) (1) Lock/Unlock/RCR Configuration 4 D0h/01h/03h Block Address Notes: (1) Block Address refers to RCR configuration data only when the 60h command sequence is used to set RCR register combined with 03h subsequent command. (2) For the third and fourth command sequences, the Block Address must be the same. (3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h commands should be less than 20us. And here is a log comparison of a simple (destructive) flash test without and with the workaround. diff without-numonyx-workaround.log with-numonyx-workaround.log -U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47) +U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19) CPU: Freescale MCF5484 CPU CLK 200 MHz BUS CLK 100 MHz Board: Macq Electronique ME2060 I2C: ready DRAM: 64 MiB FLASH: 32 MiB In: serial Out: serial Err: serial Net: FEC0, FEC1 -> flinfo Bank # 1: CFI conformant FLASH (16 x 16) Size: 32 MB in 259 Sectors Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922 Erase timeout: 4096 ms, write timeout: 1 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Sector Start Addresses: FE000000 RO FE008000 RO FE010000 RO FE018000 RO FE020000 RO FE040000 RO FE060000 RO FE080000 RO FE0A0000 RO FE0C0000 RO ... FFF80000 RO FFFA0000 RO FFFC0000 RO FFFE0000 RO -> protect off all Un-Protect Flash Bank # 1 ................... done -> erase all Erase Flash Bank # 1 ................... done -> cp.b 1000000 fe000000 2000000 -Copy to Flash... Flash not Erased +Copy to Flash... done -> Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: Cleanup flash_print_info()Stefan Roese2010-08-18-24/+27
| | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: - Extract code to detect if sector is erased into function sector_erased(). - Because of this, we don't have variable declarations inside the sector loop in flash_print_info() - Change "return" to "break" in the "if (ctrlc()) statement: This fixes a problem with the resulting output. Before this patch the output was: Sector Start Addresses: FC000000 FC020000 FC040000 => With this patch it is now: Sector Start Addresses: FC000000 FC020000 FC040000 => Signed-off-by: Stefan Roese <sr@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
* Fix printing & reading of 16-bit CFI device identifiersPhilippe De Muyter2010-08-18-4/+7
| | | | | | | | | | | | | | Fix reading and printing of CFI flashes 16-bit devices identifiers Nowadays CFI flashes have a 16-bit device identifier. U-boot still print them and read them as if they were only 8-bit wide. Fix that. Before: Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x1B After: Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x881B Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Stefan Roese <sr@denx.de>
* cfi_flash: flinfo: allow user interrupt in flash print info fnKim Phillips2010-08-18-0/+2
| | | | | | | flashes getting larger, users more impatient. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Rename getenv_r() into getenv_f()Wolfgang Denk2010-08-04-1/+1
| | | | | | | | | | | | | | | | | | | While running from flash, i. e. before relocation, we have only a limited C runtime environment without writable data segment. In this phase, some configurations (for example with environment in EEPROM) must not use the normal getenv(), but a special function. This function had been called getenv_r(), with the idea that the "_r" suffix would mean the same as in the _r_eentrant versions of some of the C library functions (for example getdate vs. getdate_r, getgrent vs. getgrent_r, etc.). Unfortunately this was a misleading name, as in U-Boot the "_r" generally means "running from RAM", i. e. _after_ relocation. To avoid confusion, rename into getenv_f() [as "running from flash"] Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-11/+7
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2010-07-14-8/+8
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| * Blackfin: bfin_nand: convert to portmux frameworkMike Frysinger2010-07-13-8/+8
| | | | | | | | | | | | | | | | Rather than bang MMRs directly, use the new portmux framework to handle the details. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand_plat: add simple GPIO framework DEV_READY optionMike Frysinger2010-07-08-0/+11
| | | | | | | | | | | | | | | | Make it easy to use GPIOs for the DEV_READY pin by using the common GPIO framework. Also make the NAND_PLAT_INIT() define optional. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* | NAND: add Toshiba TC58NVG0 identifierFlorian Fainelli2010-07-08-0/+1
| | | | | | | | | | | | | | The Toshiba TC58NVG0* parts are 128Mbytes x 8 bits 3.3V parts with the 0xD1 identifier. Add these to the list of known devices IDs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | NAND: show manufacturer and device ID for unknown chipsFlorian Fainelli2010-07-08-1/+5
|/ | | | | | | | When the NAND part is not supported, it is useful to show the manufacturer and device ID to help debugging and reporting. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* sf: move useful messages from debug to printfMike Frysinger2010-06-30-16/+22
| | | | | | | | | | At the moment, the default SPI flash subsystem is quite terse. Errors and successes both result in a generic message. So move the useful errors and useful successes to printf output by default. While we're here, also convert the messages to use print_size(). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* spi_flash: support old STMicro parts with RESThomas Chou2010-06-30-0/+22
| | | | | | | | Some old STMicro parts do not support JEDEC ID (0x9f). This patch uses RES (0xab) to get Electronic ID and translates it to JEDEC ID. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Mike Frysinger <vapier@gentoo.org>
* UBI: initialise update markerPeter Horton2010-06-23-0/+1
| | | | | | | | | | | | | | UBI: initialise update marker The in kernel copy of a volume's update marker is not initialised from the volume table. This means that volumes where an update was unfinnished will not be treated as "forbidden to use". This is basically that the update functionality was broken. Signed-off-by: Peter Horton <zero@colonel-panic.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Stefan Roese <sr@denx.de>
* Blackfin: nand: drain the write buffer before returningAndrew Caldwell2010-05-26-1/+6
| | | | | | | | | | | | | The current Blackfin nand write function fills up the write buffer but returns before it has had a chance to drain. On faster systems, this isn't a problem as the operation finishes before the ECC registers are read, but on slower systems the ECC may be incomplete when the core tries to read it. So wait for the buffer to drain once we're done writing to it. Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* UBI: Ensure that "background thread" operations are really executedStefan Roese2010-05-19-2/+7
| | | | | | | | | | | | The current U-Boot UBI implementation is copied from Linux. In this porting the UBI background thread was not handled correctly. Upon write operations ubi_wl_flush() makes sure, that all queued operations, like page-erase, are completed. But this is missing for read operations. This patch now makes sure that such operations (like scrubbing upon bit-flip errors) are not queued, but executed directly. Signed-off-by: Stefan Roese <sr@denx.de>
* drivers/mtd/spi/eeprom_m95xxx.c: add missing error checkingAlbin Tonnerre2010-04-09-0/+6
| | | | Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
* cfi_flash: reset timer in flash status checkThomas Chou2010-04-07-0/+2
| | | | | | | | | | | | | | | | | This patch adds reset_timer() before the flash status check waiting loop. Since the timer is basically running asynchronous to the cfi code, it is possible to call get_timer(0), then only a few _SYSCLK_ cycles later an interrupt is generated. This causes timeout even though much less time has elapsed. So the timer period registers should be reset before get_timer(0) is called. There is similar usage in nand_base.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-29-1/+4
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| * cfi_flash: precision and underflow problem in tout calculationRenato Andreola2010-03-25-1/+4
| | | | | | | | | | | | | | | | | | With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000. Signed-off-by: Renato Andreola <renato.andreola@imagos.it> Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'next' of git://www.denx.de/git/u-boot-cfi-flash into nextWolfgang Denk2010-03-29-7/+86
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| * | cfi flash: add status polling method for amd flashThomas Chou2010-03-26-7/+86
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds status polling method to offer an alternative to data toggle method for amd flash chips. This patch is needed for nios2 cfi flash interface, where the bus controller performs 4 bytes read cycles for a single byte read instruction. The data toggle method can not detect chip busy status correctly. So we have to poll DQ7, which will be inverted when the chip is busy. This feature is enabled with the config def, CONFIG_SYS_CFI_FLASH_STATUS_POLL Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* | at91: add hwecc method for nandNikolay Petukhov2010-03-23-0/+301
| | | | | | | | | | | | | | This is a patch to use the hardware ECC controller of the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
* | TI: Davinci: NAND Driver CleanupCyril Chemparathy2010-03-23-59/+69
|/ | | | | | | Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy <cyril@ti.com>
* mod change 755 => 644 for multiple filesThomas Weber2010-03-21-0/+0
| | | | | | | | I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' Signed-off-by: Thomas Weber <swirl@gmx.li> Add some more: neither Makefile nor config.mk need execute permissions. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-3/+1
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ] fix monitor protection for CONFIG_MONITOR_IS_IN_RAMWolfgang Wegner2010-03-04-1/+2
| | | | | | | | | | For platforms with flash below ram addresses, the current check to activate monitor protection is wrong/insufficient. This patch fixes CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for this configuration. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2010-02-03-17/+18
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| * CFI: fix eraseregions numblocksLadislav Michl2010-02-02-17/+18
| | | | | | | | | | | | | | | | | | | | eraseregions numblocks was sometimes one less than actual, possibly producing erase regions with zero blocks. As MTD code touches eraseregions only if numeraseregions is greater that zero, allocate eraseregions only for non uniform erase size flash. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Nand mxc_nand add v1.1 controller supportJohn Rigby2010-01-27-71/+546
|/ | | | | | | | Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Scott Wood <scottwood@freescale.com>
* SPEAr : nand driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+125
| | | | | | | | SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : smi driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+524
| | | | | | | | SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* MXC: Add large page oob layout for i.MX31 NAND controller.Magnus Lilja2010-01-19-0/+12
| | | | | | | | | | | | | Import the large page oob layout from Linux mxc_nand.c driver. The CONFIG_SYS_NAND_LARGEPAGE option is used to activate the large page oob layout. Run time detection is not supported as this moment. This has been tested on the i.MX31 PDK board with a large page NAND device. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* mxc_nand: Update driver to work with i.MX31.Magnus Lilja2010-01-19-3/+31
| | | | | | Tested on i.MX31 Litekit. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+13
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| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-14/+11
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | Davinci: davinci_nand.c performance enhancmentsNick Thompson2010-01-06-54/+146
|/ | | | | | | | | | | Introduces various optimisations that approximately triple the read data rate from NAND when run on da830evm. Most of these optimisations depend on the endianess of the machine and most of them are very similar to optimisations already present in the Linux Kernel. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
* Merge branch 'next' of ../nextWolfgang Denk2009-12-15-159/+855
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| * common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-4/+0
| | | | | | | | | | | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
| * Merge branch 'master' into nextWolfgang Denk2009-12-07-1/+1
| |\ | | | | | | | | | | | | | | | | | | Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * \ Merge branch 'master' into nextWolfgang Denk2009-12-05-1/+341
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | NAND: Add Support for 4K page size in DaVinci NAND driverSandeep Paulraj2009-11-20-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NAND devices with a page size of 4K in the DaVinci NAND driver. The layout matches the layout that TI uses for 4K page size NAND devices in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | S3C2410 NAND Flash Add Missing FunctionHui.Tang2009-11-18-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add nand_read_buf() for S3C2410 NAND SPL. In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip, so nand->select_chip should also be initialized. Signed-off-by: Hui.Tang <zetalabs@gmail.com>
| * | | NAND: Update read_read_subpage API checkSandeep Paulraj2009-11-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates a check condition in the NAND driver. The check condition is similat to what is in linux/next. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | Flex-OneNAND driver supportAmul Kumar Saha2009-11-13-98/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Flex-OneNAND devices. Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com> Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
| * | | fsl_elbc_nand: remove the bbt descriptors relocation fixupMingkai Hu2009-11-13-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 66372fe2 manually relocated the bbt pattern pointer, which can be removed by using full relocation. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
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