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* UBI: initialise update markerPeter Horton2010-06-23-0/+1
| | | | | | | | | | | | | | UBI: initialise update marker The in kernel copy of a volume's update marker is not initialised from the volume table. This means that volumes where an update was unfinnished will not be treated as "forbidden to use". This is basically that the update functionality was broken. Signed-off-by: Peter Horton <zero@colonel-panic.org> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Stefan Roese <sr@denx.de>
* Blackfin: nand: drain the write buffer before returningAndrew Caldwell2010-05-26-1/+6
| | | | | | | | | | | | | The current Blackfin nand write function fills up the write buffer but returns before it has had a chance to drain. On faster systems, this isn't a problem as the operation finishes before the ECC registers are read, but on slower systems the ECC may be incomplete when the core tries to read it. So wait for the buffer to drain once we're done writing to it. Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* UBI: Ensure that "background thread" operations are really executedStefan Roese2010-05-19-2/+7
| | | | | | | | | | | | The current U-Boot UBI implementation is copied from Linux. In this porting the UBI background thread was not handled correctly. Upon write operations ubi_wl_flush() makes sure, that all queued operations, like page-erase, are completed. But this is missing for read operations. This patch now makes sure that such operations (like scrubbing upon bit-flip errors) are not queued, but executed directly. Signed-off-by: Stefan Roese <sr@denx.de>
* drivers/mtd/spi/eeprom_m95xxx.c: add missing error checkingAlbin Tonnerre2010-04-09-0/+6
| | | | Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
* cfi_flash: reset timer in flash status checkThomas Chou2010-04-07-0/+2
| | | | | | | | | | | | | | | | | This patch adds reset_timer() before the flash status check waiting loop. Since the timer is basically running asynchronous to the cfi code, it is possible to call get_timer(0), then only a few _SYSCLK_ cycles later an interrupt is generated. This causes timeout even though much less time has elapsed. So the timer period registers should be reset before get_timer(0) is called. There is similar usage in nand_base.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-29-1/+4
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| * cfi_flash: precision and underflow problem in tout calculationRenato Andreola2010-03-25-1/+4
| | | | | | | | | | | | | | | | | | With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000. Signed-off-by: Renato Andreola <renato.andreola@imagos.it> Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'next' of git://www.denx.de/git/u-boot-cfi-flash into nextWolfgang Denk2010-03-29-7/+86
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| * | cfi flash: add status polling method for amd flashThomas Chou2010-03-26-7/+86
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds status polling method to offer an alternative to data toggle method for amd flash chips. This patch is needed for nios2 cfi flash interface, where the bus controller performs 4 bytes read cycles for a single byte read instruction. The data toggle method can not detect chip busy status correctly. So we have to poll DQ7, which will be inverted when the chip is busy. This feature is enabled with the config def, CONFIG_SYS_CFI_FLASH_STATUS_POLL Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Stefan Roese <sr@denx.de>
* | at91: add hwecc method for nandNikolay Petukhov2010-03-23-0/+301
| | | | | | | | | | | | | | This is a patch to use the hardware ECC controller of the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
* | TI: Davinci: NAND Driver CleanupCyril Chemparathy2010-03-23-59/+69
|/ | | | | | | Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy <cyril@ti.com>
* mod change 755 => 644 for multiple filesThomas Weber2010-03-21-0/+0
| | | | | | | | I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' Signed-off-by: Thomas Weber <swirl@gmx.li> Add some more: neither Makefile nor config.mk need execute permissions. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-3/+1
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ] fix monitor protection for CONFIG_MONITOR_IS_IN_RAMWolfgang Wegner2010-03-04-1/+2
| | | | | | | | | | For platforms with flash below ram addresses, the current check to activate monitor protection is wrong/insufficient. This patch fixes CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for this configuration. Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-cfi-flashWolfgang Denk2010-02-03-17/+18
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| * CFI: fix eraseregions numblocksLadislav Michl2010-02-02-17/+18
| | | | | | | | | | | | | | | | | | | | eraseregions numblocks was sometimes one less than actual, possibly producing erase regions with zero blocks. As MTD code touches eraseregions only if numeraseregions is greater that zero, allocate eraseregions only for non uniform erase size flash. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | Nand mxc_nand add v1.1 controller supportJohn Rigby2010-01-27-71/+546
|/ | | | | | | | Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Scott Wood <scottwood@freescale.com>
* SPEAr : nand driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+125
| | | | | | | | SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
* SPEAr : smi driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+524
| | | | | | | | SPEAr SoCs contain a serial memory interface controller. This controller is used to interface with spi based memories. This patch adds the driver for this IP. Signed-off-by: Vipin <vipin.kumar@st.com>
* MXC: Add large page oob layout for i.MX31 NAND controller.Magnus Lilja2010-01-19-0/+12
| | | | | | | | | | | | | Import the large page oob layout from Linux mxc_nand.c driver. The CONFIG_SYS_NAND_LARGEPAGE option is used to activate the large page oob layout. Run time detection is not supported as this moment. This has been tested on the i.MX31 PDK board with a large page NAND device. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* mxc_nand: Update driver to work with i.MX31.Magnus Lilja2010-01-19-3/+31
| | | | | | Tested on i.MX31 Litekit. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+13
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| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-14/+11
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | Davinci: davinci_nand.c performance enhancmentsNick Thompson2010-01-06-54/+146
|/ | | | | | | | | | | Introduces various optimisations that approximately triple the read data rate from NAND when run on da830evm. Most of these optimisations depend on the endianess of the machine and most of them are very similar to optimisations already present in the Linux Kernel. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
* Merge branch 'next' of ../nextWolfgang Denk2009-12-15-159/+855
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| * common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-4/+0
| | | | | | | | | | | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
| * Merge branch 'master' into nextWolfgang Denk2009-12-07-1/+1
| |\ | | | | | | | | | | | | | | | | | | Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * \ Merge branch 'master' into nextWolfgang Denk2009-12-05-1/+341
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/esd/plu405/plu405.c drivers/rtc/ftrtc010.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | NAND: Add Support for 4K page size in DaVinci NAND driverSandeep Paulraj2009-11-20-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NAND devices with a page size of 4K in the DaVinci NAND driver. The layout matches the layout that TI uses for 4K page size NAND devices in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | S3C2410 NAND Flash Add Missing FunctionHui.Tang2009-11-18-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add nand_read_buf() for S3C2410 NAND SPL. In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip, so nand->select_chip should also be initialized. Signed-off-by: Hui.Tang <zetalabs@gmail.com>
| * | | NAND: Update read_read_subpage API checkSandeep Paulraj2009-11-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates a check condition in the NAND driver. The check condition is similat to what is in linux/next. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | Flex-OneNAND driver supportAmul Kumar Saha2009-11-13-98/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Flex-OneNAND devices. Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com> Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
| * | | fsl_elbc_nand: remove the bbt descriptors relocation fixupMingkai Hu2009-11-13-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 66372fe2 manually relocated the bbt pattern pointer, which can be removed by using full relocation. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
| * | | NAND: fix "raw" reads with ECC syndrome layoutsDavid Brownell2009-11-13-4/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome based page read/write routines store ECC, and possibly other "OOB" data, right after each chunk of ECC'd data. With ECC chunk size of 512 bytes and a large page (2KiB) NAND, the layout is: data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines use a traditional layout -- data OOB, disregarding the prepad and postpad values -- so when they're used with that type of ECC hardware, those calls mix up the data and OOB. Which means, in particular, that bad block tables won't be found on startup, with data corruption and related chaos ensuing. The current syndrome-based drivers in mainline all seem to use one chunk per page; presumably they haven't noticed such bugs. Fix this, by adding read/write page_raw_syndrome() routines as siblings of the existing non-raw routines; "raw" just means to bypass the ECC computations, not change data and OOB layout. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * | | NAND: Don't walk past end of oobfree[]Sandeep Paulraj2009-11-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When computing oobavail from the list of free areas in the OOB, don't assume there will always be an unused slot at the end. This syncs up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Update check condition for nand_read_page_hwecc APISandeep Paulraj2009-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch updates the check condition for determining whether the ECC corrections has failed. This makes it similar to what is in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Updating comments/explanations in the NAND driverSandeep Paulraj2009-11-13-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch updates the comments and explanations for the arguments to various functions. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Subpage shift for ecc_steps equal to 16Sandeep Paulraj2009-11-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally part of Thomas Gleixner's patch for adding support for 4KiB pages. This is not part of the U-Boot NAND driver so updating the driver with this to sync up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Remove commented out codeSandeep Paulraj2009-11-13-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Patch removes already commented out dead code Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Correct the "chip_shift" calculationSandeep Paulraj2009-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the "chip_shift" calculation in the NAND driver. This is being done to sync up the NAND driver with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | | NAND: Update to support 64 bit device sizeSandeep Paulraj2009-11-13-28/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | | nand: Fix access to last block in NAND devicesStefan Roese2009-12-11-2/+2
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | Currently, the last block of NAND devices can't be accessed. This patch fixes this issue by correcting the boundary checking (off-by-one error). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
* | | Fix computation in nand_util.c:get_len_incl_badDaniel Hobi2009-12-07-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | Depending on offset, flash size and the number of bad blocks, get_len_incl_bad may return a too small value which may lead to: 1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the bad block aware read/write code. This may hurt performance, but does not have any adverse effects. 2) If there are bad blocks, the nand_{read,write}_skip_bad may choose the bad block unaware read/write code (if len_incl_bad == *length) which leads to corrupted data. Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
* | sf: fix stmicro offset setup while erasingMike Frysinger2009-11-22-1/+2
| | | | | | | | | | Reported-by: Peter Gombos <gombos@protecta.hu> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | sf: new driver for Winbond W25X16/32/64 devicesJason McMullan2009-11-22-0/+339
|/ | | | | Signed-off-by: Jason McMullan <jason.mcmullan@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* cfi: Add weak default function for flash_cmd_reset()Stefan Roese2009-10-28-133/+18
| | | | | | | | | | | | Currently the CFI driver issues both AMD and Intel reset commands. This is because the driver doesn't know yet which chips are connected. This dual reset seems to cause problems with the M29W128G chips as reported by Richard Retanubun. This patch now introduces a weak default function for the CFI reset command, still with both resets. This can be overridden by a board specific version if necessary. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
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