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* driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha2014-02-03-151/+152
| | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc:mpc85xx: Add ifc nand boot support for TPL/SPLPo Liu2014-01-21-7/+24
| | | | | | | | | | | | | | | Using the TPL method for nand boot by sram was already supported. Here add some code for mpc85xx ifc nand boot. - For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec. - Use a clear function name for nand spl boot. - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c in spl/Makefile; Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* nand, gpmc: fix reading after switching eccJeroen Hofstee2014-01-17-0/+1
| | | | | | | | | | | | | | The omap_gpmc allows switching ecc at runtime. Since the NAND_SUBPAGE_READ flag is only set, it is kept when switching to hw ecc, which is not correct. This leads to calling chip->ecc.read_subpage which is not a valid pointer. Therefore clear the flag when switching ecc so reading in hw mode works again. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* sf: params: Removed flag SECT_4K for Micron N25Q128Siva Durga Prasad Paladugu2014-01-12-2/+2
| | | | | | | | | Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add CONFIG_SF_DUAL_FLASHJagannadha Sutradharudu Teki2014-01-12-5/+14
| | | | | | | This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add dual memories support - DUAL_PARALLELJagannadha Sutradharudu Teki2014-01-12-7/+12
| | | | | | | | | This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add dual memories support - DUAL_STACKEDJagannadha Sutradharudu Teki2014-01-12-11/+57
| | | | | | | | | This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ops: Unify read_ops bank configurationJagannadha Sutradharudu Teki2014-01-12-8/+5
| | | | | | Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Code cleanupsJagannadha Sutradharudu Teki2014-01-12-13/+8
| | | | | | | - comment typo's - func args have a proper names Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Divide flash register ops from QEB codeJagannadha Sutradharudu Teki2014-01-11-53/+77
| | | | | | | QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Enable macronix quad read/write cmds supportJagannadha Sutradharudu Teki2014-01-11-4/+4
| | | | | | | | | Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add macronix set QEB supportJagannadha Sutradharudu Teki2014-01-11-0/+35
| | | | | | | This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Discover read dummy_byteJagannadha Sutradharudu Teki2014-01-11-7/+30
| | | | | | | Discovered the read dummy_byte based on the configured read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add QUAD_IO_FAST read supportJagannadha Sutradharudu Teki2014-01-11-0/+3
| | | | | | This patch adds support QUAD_IO_FAST read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Separate the flash params tableJagannadha Sutradharudu Teki2014-01-11-145/+135
| | | | | | | | Moved the flash params table from sf_probe.c and placed on to sf_params.c, hence flash params file will alter based on new addons. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Enable RD_FULL and WR_QPPJagannadha Sutradharudu Teki2014-01-11-30/+30
| | | | | | | | | This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Set quad enable bit supportJagannadha Sutradharudu Teki2014-01-11-2/+62
| | | | | | | | | | | | | This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ops: Add configuration register writing supportJagannadha Sutradharudu Teki2014-01-11-0/+24
| | | | | | | | | This patch provides support to program a flash config register. Configuration register contains the control bits used to configure the different configurations and security features of a device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add quad read/write commands supportJagannadha Sutradharudu Teki2014-01-11-86/+96
| | | | | | | | This patch add quad commands support like - QUAD_PAGE_PROGRAM => for write program - QUAD_OUTPUT_FAST ->> for read program Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add extended read commands supportJagannadha Sutradharudu Teki2014-01-11-86/+108
| | | | | | | | | | | Current sf uses FAST_READ command, this patch adds support to use the different/extended read command. This implementation will determine the fastest command by taking the supported commands from the flash and the controller, controller is always been a priority. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-1/+8
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| * driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: add support for MX25L2006ELuka Perkov2013-12-18-0/+1
| | | | | | | | | | | | | | Add support for Macronix MX25L2006E SPI flash. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: probe: Hex values are in lower caseLuka Perkov2013-12-18-1/+1
| | | | | | | | | | | | | | | | All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | mtd: nand: omap: fix ecc ops assignment when changing eccNikita Kiryanov2013-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | mtd: nand: omap: fix sw->hw->sw ecc switchNikita Kiryanov2013-12-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values into the current nand chip's ecc.layout struct. This is done under the assumption that the struct exists only to store values, so it is OK to overwrite it, but there is at least one situation where this assumption is incorrect: When switching to 1 bit hamming code sw ecc, the job of assigning layout data is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a pointer to an existing struct prefilled with the appropriate values. This struct doubles as both data and layout definition, and therefore shouldn't be overwritten, but on the next switch to hardware ecc, this is exactly what's going to happen. The next time the user switches to software ecc, they're going to get a messed up ecc layout. Prevent this and possible similar bugs by explicitly using the private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | nand_util.c: Use '%zd' for length in nand_unlock debug printTom Rini2013-12-17-1/+1
| | | | | | | | | | | | | | length is size_t so needs to be '%zd' not '%d' to avoid warnings. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
* | mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.sizeNikita Kiryanov2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way software ECC is configured, both during boot, and during ecc switch, in a way that is not backwards compatible with older systems: Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring for software ecc, relying on nand_scan_tail() to select a default for ecc.size (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize, which is likely to not be 256. Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert to the original behavior. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap_gpmc: cosmetic: Fix indentationStefan Roese2013-12-17-43/+45
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: wrap some long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand: omap: fix ecc-layout for HAM1 ecc-schemepekon gupta2013-12-17-2/+6
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
* drivers/mtd: descend into sub directories only when it is necessaryMasahiro Yamada2013-12-13-6/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-12-10-5/+3
|\ | | | | | | | | | | | | | | Conflicts: board/samsung/trats2/trats2.c include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-12-10-153/+530
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/cpu/armv7/rmobile/Makefile doc/README.scrapyard Needed manual fix: arch/arm/cpu/armv7/omap-common/Makefile board/compulab/cm_t335/u-boot.lds
| * | at91: nand: switch atmel_nand to generic GPIO APIAndreas Bießmann2013-12-09-5/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Tested-by: Jens Scharsig (BuS Elektronik)<esw@bus-elektronik.de> Acked-by: Scott Wood <scottwood@freescale.com>
* | | Merge branch 'spi' of git://git.denx.de/u-boot-x86Tom Rini2013-12-10-5/+508
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| * | | sandbox: spi: Add new SPI flash driverMike Frysinger2013-12-09-1/+487
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a SPI flash driver which simulates SPI flash clients. Currently supports the bare min that U-Boot requires: you can probe, read, erase, and write. Should be easy to extend to make it behave more exactly like a real SPI flash, but this is good enough to merge now. sjg@chromium.org added a README and tidied up code a little. Added a required map_sysmem() for sandbox. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT nodeSimon Glass2013-12-09-4/+21
| | |/ | |/| | | | | | | | | | | | | | | | This allows us to put the SPI flash chip inside the SPI interface node, with U-Boot finding the correct bus and chip select automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | powerpc: spiflash:Add corenet devices support in eSPI SPLPriyanka Jain2013-12-04-0/+5
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Existing eSPI SPL framework assumes booting from spi-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-12-02-2/+2
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| * | Driver/IFC: Move Freescale IFC driver to a common driverYork Sun2013-11-25-2/+2
| |/ | | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
* | mtd: nand: omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-schemepekon gupta2013-11-21-9/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed CONFIG_xx used for selecting NAND ecc-schemes. This patch aims at solving following issues. 1) Currently ecc-scheme is tied to SoC platform, which prevents user to select other ecc-schemes also supported in hardware. like; - most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW). - most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware supports BCH16 ecc-scheme also. 2) Different platforms use different CONFIG_xx to select ecc-schemes, which adds confusion for user while migrating platforms. - *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only 8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW) whereas ELM hardware engine supports other ecc-schemes also like; BCH4, and BCH16 (in future). - *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW). - *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w library Thus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency on SoC platform and NAND driver. And user can select ecc-scheme independently foreach board. However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand) Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: enable BCH ECC scheme using ELM for generic platformpekon gupta2013-11-21-125/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours +-----------------------------------+-----------------+-----------------+ |ECC Scheme | ECC Calculation | Error Detection | +-----------------------------------+-----------------+-----------------+ |OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine | |OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library | +-----------------------------------+-----------------+-----------------+ Current implementation limits the BCH8_CODE_HW only for AM33xx device family. (using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have ELM hardware module, and can support ECC error detection using ELM. This patch - removes CONFIG_AM33xx Thus this driver can be reused by all devices having ELM h/w engine. - adds omap_select_ecc_scheme() A common function to handle ecc-scheme related configurations. This can be used both during device-probe and via user-space u-boot commads to change ecc-scheme. During device probe ecc-scheme is selected based on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8 - enables CONFIG_BCH S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW is enabled by CONFIG_BCH. - enables CONFIG_SYS_NAND_ONFI_DETECTION for auto-detection of ONFI compliant NAND devices - updates following README doc doc/README.nand board/ti/am335x/README doc/README.omap3 Signed-off-by: Pekon Gupta <pekon@ti.com> [scottwood@freescale.com: fixed unused variable warning] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx ↵pekon gupta2013-11-21-1/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | platforms ELM hardware engine which is used for ECC error detection, is present on all latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM driver should be moved to common drivers/mtd/nand/ folder so that all SoC having on-chip ELM hardware engine can re-use it. This patch has following changes: - mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h - mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c - update Makefiles - update #include <asm/elm.h> - add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c and include in all board configs using AM33xx SoC platform. Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: atmel_nand: use dev_xxx instead of printkWu, Josh2013-11-21-11/+11
| | | | | | | | Signed-off-by: Josh Wu <josh.wu@atmel.com>
* | mtd: atmel_nand: don't print bit correction message in driverWu, Josh2013-11-21-2/+2
| | | | | | | | | | | | | | Since for some MLC nand, bit errors happened too often. Just disable it to avoid noise Signed-off-by: Josh Wu <josh.wu@atmel.com>
* | mtd: atmel_nand: enable PMECC support for 8k bytes page NAND flashWu, Josh2013-11-21-1/+9
| | | | | | | | | | | | increase the delay to 75us to support the 8k bytes page nand flash Signed-off-by: Josh Wu <josh.wu@atmel.com>
* | mtd/ifc: Add support of 8K page size NAND flashPrabhakar Kushwaha2013-11-21-2/+83
| | | | | | | | | | | | | | | | | | | | | | | | Current IFC driver supports till 4K page size NAND flash. Add support of 8K NAND flash - Program Spare region size in csor_ext - Add nand_ecclayout for 4 bit & 8 bit ecc - Defines constants - Add support of 8K NAND boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Liu Po <po.liu@freescale.com>
* | mtd: move & update nand_ecclayout structure (plus board changes)Prabhakar Kushwaha2013-11-21-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_ecclayout is present in mtd.h at Linux. Move this structure to mtd.h to comply with Linux. Also, increase the ecc placement locations to 640 to suport device having writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone up to 640 bytes and consequently the maximum ecc placement locations have also gone up to 640. Changes from Prabhabkar's version (squashed into one patch to preserve bisectability): - Added _LARGE to MTD_MAX_*_ENTRIES This makes the names match current Linux source, and resolves a conflict between http://patchwork.ozlabs.org/patch/280488/ and http://patchwork.ozlabs.org/patch/284513/ The former was posted first and is closer to matching Linux, but unlike Linux it does not add _LARGE to the names. The second adds _LARGE to one of the names, and depends on it in a subsequent patch (http://patchwork.ozlabs.org/patch/284512/). - Made max oobfree/eccpos configurable, and used this on tricorder, alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build for me without doing so, due to a size increase). On tricorder SPL, this saves 2576 bytes (and makes the SPL build again) versus the new default of 640 eccpos and 32 oobfree, and saves 336 bytes versus the old default of 128 eccpos and 8 oobfree. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Vipin Kumar <vipin.kumar@st.com> [scottwood@freescale.com: changes as described above] Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Thomas Weber <weber@corscience.de> Cc: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Cc: Stefan Roese <sr@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
* | driver/mtd/ifc: Read Status while programming NAND flashPrabhakar Kushwaha2013-11-13-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as per controller description, "While programming a NAND flash, status read should never skipped. Because it may happen that a new command is issued to the NAND Flash, even when the device has not yet finished processing the previous request. This may result in unpredictable behaviour." IFC controller never polls for R/B signal after command send. It just return control to software. This behaviour may not occur with NAND flash access. because new commands are sent after polling R/B signal. But it may happen in scenario where GPCM-ASIC and NAND flash device are working simultaneously. Update the controller driver to take care of this requirement Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
generated by cgit v1.1 at 2024-11-30 02:46:32 +0000