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* lib: consolidate hang()Andreas Bießmann2013-05-01-9/+0
| | | | | | | | | Delete all occurrences of hang() and provide a generic function. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Modify check around puts() in hang.c slightly] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-04-15-572/+1072
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| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-12-43/+155
| |\ | | | | | | | | | | | | Conflicts: drivers/video/exynos_fb.c
| * | kirkwood_nand: allow usage of NAND_ECC_SOFT_BCHGerlando Falauto2013-04-12-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_NAND_ECC_BCH is set use 4-bit error correction code instead of the 1-bit error correction code on the NAND device. Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | arm: Remove support for unused s3c64xxBenoît Thébaudeau2013-04-12-356/+4
| | | | | | | | | | | | | | | | | | | | | | | | Following the removal of the smdk6400 board, the s3c64xx SoC becomes unused, so remove associated code. It will still be possible to restore it later from the Git history if necessary. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | nand: mxc: Switch NAND SPL to generic SPLBenoît Thébaudeau2013-04-12-5/+597
| | | | | | | | | | | | | | | | | | | | | | | | | | | This also fixes support for mx31pdk and tx25, which had been broken by commit e05e5de7fae5bec79617e113916dac6631251156. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | nand: mxc: Use appropriate page number in syndrome functionsBenoît Thébaudeau2013-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome functions should use the page number passed as argument instead of the page number saved upon NAND_CMD_READ0. This does not make any difference if the NAND_NO_AUTOINCR option is set, but otherwise this fixes accesses to the wrong pages. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | nand: mxc: Fix debug trace in mxc_nand_read_oob_syndrome()Benoît Thébaudeau2013-04-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page number indicated in the debug trace of mxc_nand_read_oob_syndrome() did not match the page being worked on. By the way, replace the GCC-specific __FUNCTION__ with __func__. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com>
| * | nand: mxc: Add support for i.MX5Benoît Thébaudeau2013-04-12-11/+108
| | | | | | | | | | | | | | | | | | Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | nand: mxc: Prepare to add support for i.MX5Benoît Thébaudeau2013-04-12-46/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some abstraction to NFC definitions so that some parts of the current code can also be used for future i.MX5 code. Clean up a few things by the way. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Scott Wood <scottwood@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | mtd: nand: mxc_nand: Fix is_16bit_nand()Fabio Estevam2013-04-12-34/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently is_16bit_nand() is a per SoC function and it decides the bus nand width by reading some boot related registers. This method works when NAND is the boot medium, but does not work if another boot medium is used. For example: booting from a SD card and then using NAND to store the environment variables, would lead to the following error: NAND bus width 16 instead 8 bit No NAND device found!!! 0 MiB Use CONFIG_SYS_NAND_BUSWIDTH_16BIT symbol to decide the bus width. If it is defined in the board file, then consider 16-bit NAND bus-width, otherwise assume 8-bit NAND is used. This also aligns with Documentation/devicetree/bindings/mtd/nand.txt, which states: nand-bus-width : 8 or 16 bus width if not present 8 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | mtd: nand: Introduce CONFIG_SYS_NAND_BUSWIDTH_16BITFabio Estevam2013-04-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_SYS_NAND_BUSWIDTH_16BIT option so that other NAND controller drivers could use it when a 16-bit NAND is deployed. drivers/mtd/nand/ndfc has CONFIG_SYS_NDFC_16BIT, so just rename it, so that other NAND drivers could reuse the same symbol. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
| * | omap_gpmc: add support for hw assisted BCH8Andreas Bießmann2013-04-08-91/+276
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel states: ---8<--- The OMAP3 GPMC hardware BCH engine computes remainder polynomials, it does not provide automatic error location and correction: this step is implemented using the BCH library. --->8--- And we do so in u-boot. This implementation uses the same layout for BCH8 but it is fix. The current provided layout does only work with 64 Byte OOB. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Ilya Yanok <ilya.yanok@cogentembedded.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Mansoor Ahamed <mansoor.ahamed@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | omap_gpmc: change nandecc commandAndreas Bießmann2013-04-08-26/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
| * | asm/omap_gpmc.h: consolidate common definesAndreas Bießmann2013-04-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | | Revert "mtd: cfi_flash: Fix CFI flash driver for 8-bit bus support"Stefan Roese2013-04-12-55/+23
| | | | | | | | | | | | | | | | | | This reverts commit 239cb9d904cfa8ab50d840a47b3306189d695c75. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Revert "cfi_flash: Use uintptr_t for casts from u32 to void *"Stefan Roese2013-04-12-1/+1
| |/ |/| | | | | | | | | This reverts commit 81a4f7098ba137ea1961cb997ca16d57de2b3483. Signed-off-by: Stefan Roese <sr@denx.de>
* | ubi: ubifs: Turn off verbose printsJoe Hershberger2013-04-11-6/+12
| | | | | | | | | | | | The prints are out of control. SILENCE! Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | ubi: Fix broken cleanup code in attach_by_scanningJoe Hershberger2013-04-11-4/+5
| | | | | | | | | | | | | | The unwind code was not reversing operations correctly and was causing a hang on any error condition. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* | nand: Extend nand_(read|write)_skip_bad with *actual and limit parametersTom Rini2013-04-10-8/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We make these two functions take a size_t pointer to how much space was used on NAND to read or write the buffer (when reads/writes happen) so that bad blocks can be accounted for. We also make them take an loff_t limit on how much data can be read or written. This means that we can now catch the case of when writing to a partition would exceed the partition size due to bad blocks. To do this we also need to make check_skip_len count not just complete blocks used but partial ones as well. All callers of nand_(read|write)_skip_bad are adjusted to call these with the most sensible limits available. The changes were started by Pantelis and finished by Tom. Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com> Signed-off-by: Tom Rini <trini@ti.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-cfi-flashTom Rini2013-04-04-23/+78
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| * | cfi_flash: Use uintptr_t for casts from u32 to void *Stefan Roese2013-04-04-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes this build warning: Configuring for qemu_mips64 - Board: qemu-mips64, Options: SYS_BIG_ENDIAN text data bss dec hex filename 215344 13082 218720 447146 6d2aa qemu_mips64/u-boot cfi_flash.c: In function 'flash_map': cfi_flash.c:217:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| * | mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devicesJagannadha Sutradharudu Teki2013-04-02-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch addjusted the write buffer size for M29EW devices those are operated in 8-bit mode. The M29EW devices seem to report the CFI information wrong when it's in 8 bit mode. There's an app note from Numonyx on this issue and there's a patch in the open source as well for Linux, but it doesn't seem to be in mainline. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | mtd: cfi_flash: Fix CFI flash driver for 8-bit bus supportaaron.williams@caviumnetworks.com2013-04-02-23/+55
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is based on that patch from aaron.williams@caviumnetworks.com with same commit title. pulled the same code changes into current u-boot tree. http://patchwork.ozlabs.org/patch/140863/ http://lists.denx.de/pipermail/u-boot/2011-April/089606.html This patch corrects the addresses used when working with Spansion/AMD FLASH chips. Addressing for 8 and 16 bits is almost identical except in the 16-bit case the LSB of the address is always 0. The confusion arose because the addresses in the datasheet for 16-bit mode are word addresses but this code assumed it was byte addresses. I have only been able to test this on our Octeon boards which use either an 8-bit or 16-bit bus. I have not tested the case where there's an 8-bit part on a 16-bit bus. This patch also adds some delays as suggested by Spansion. If a part can be both 8 and 16-bits, it forces it to work in 8-bit mode if an 8-bit bus is detected. Apart from the pulled changes, fixed few minor code cleanups and tested on 256M29EW, 512M29EW flashes. Before this fix: --------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0xFF, Device ID: 0xFF Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes After this fix: -------------- Bank # 1: CFI conformant flash (8 x 8) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x89, Device ID: 0x7E2301 Erase timeout: 4096 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 1024 bytes Signed-off-by: Aaron Williams <aaron.williams@caviumnetworks.com> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | Consolidate bool typeYork Sun2013-04-01-2/+0
|/ | | | | | | | | | | | | 'bool' is defined in random places. This patch consolidates them into a single header file include/linux/types.h, using stdbool.h introduced in C99. All other #define, typedef and enum are removed. They are all consistent with true = 1, false = 0. Replace FALSE, False with false. Replace TRUE, True with true. Skip *.py, *.php, lib/* files. Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-28-0/+6
|\ | | | | | | | | | | | | Conflicts: drivers/spi/tegra20_sflash.c include/fdtdec.h lib/fdtdec.c
| * sf: winbond: add W25Q32DWAllen Martin2013-03-25-0/+5
| | | | | | | | | | | | | | | | Add support for Winbond W25Q32DW 32Mbit part Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * am33xx: Add required includes to some omap/am33xx codeTom Rini2013-03-24-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | - In arch/arm/cpu/armv7/omap-common/timer.c, drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files that the driver needs but had been relying on <config.h> to bring in. - In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h> - In am335x_evm.h and pcm051.h don't globally include <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h> as that is the only include which defines things the config uses. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
* | sf: Enable FDT-based configuration and memory mappingSimon Glass2013-03-19-1/+45
| | | | | | | | | | | | | | Enable device tree control of SPI flash, and use this to implement memory-mapped SPI flash, which is supported on Intel chips. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sf: Respect maximum SPI write sizeSimon Glass2013-03-19-2/+8
| | | | | | | | | | | | | | | | Some SPI flash controllers (e.g. Intel ICH) have a limit on the number of bytes that can be in a write transaction. Support this by breaking the writes into multiple transactions. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sf: Use spi_flash_alloc() in each SPI flash driverSimon Glass2013-03-19-52/+8
| | | | | | | | | | | | | | | | Rather than each device having its own way to allocate a SPI flash structure, use the new allocation function everywhere. This will make it easier to extend the interface without breaking devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sf: Add spi_flash_alloc() to create a new SPI flash structSimon Glass2013-03-19-0/+25
|/ | | | | | | | | | At present it is difficult to extend the SPI flash structure since all devices allocate it themselves, and few of them zero all fields. Add a new function spi_flash_alloc() which can be used by SPI devices to perform this allocation, and thus ensure that all devices can better cope with SPI structure changes. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-1/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * mtd: nand: Check if NAND is locked tight before lock cmdsJoe Hershberger2013-02-22-1/+18
| | | | | | | | | | | | | | | | | | If the NAND is locked tight, commands such as lock and unlock will not work, but the NAND chip may not report an error. Check the lock tight status before attempting such operations so that an error status can be reported if we know the operation will not succeed. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| * kmeter1_nand: allow uasge of NAND_ECC_SOFT_BCHHolger Brunck2013-02-15-0/+4
| | | | | | | | | | | | | | | | | | If CONFIG_NAND_ECC_BCH is set we use 4-bit error corretion code instead of the 1-bit error correction code on the NAND device within this driver. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Acked-by: Scott Wood <scottwood@freescale.com>
* | SPL: ONENAND: Fix onenand_spl_load_image implementation.Enric Balletbo i Serra2013-03-08-8/+6
|/ | | | | | | | | | Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation doesn't work. This patch fixes this function changing the read loop and reading the onenand blocks from page to page. Tested with various IGEP based boards with a OneNAND from Numonyx. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
* sf: stmicro: Add support for N25Q256AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q256A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q32AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q32A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q32Jagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q32 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: Add support for N25Q64AJagannadha Sutradharudu Teki2013-02-06-0/+6
| | | | | | | Add support for Numonyx N25Q64A SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: winbond: Add W25Q64WJagannadha Sutradharudu Teki2013-02-06-0/+5
| | | | | | | | Add support for Winbond's W25Q64W SPI flash. This device is used on xilinx zynq emulation platform. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: spansion: Correct the first byte of idcode1 for S25FL256S partJagannadha Sutradharudu Teki2013-02-06-1/+1
| | | | | | | This patch corrected the first byte of idcode1 for S25FL256S SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* sf: stmicro: add support for N25Q064Jagannadha Sutradharudu Teki2013-02-04-0/+6
| | | | | | Add support for Numonyx N25Q064 SPI flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* cfi_flash: Report Advanced Sector Protection (PPB) with flinfo cmdStefan Roese2013-01-10-0/+2
| | | | | | | | | | | | | | | | | | | | Report the usage of the Advanced Sector Protection (PPB) to the user upon 'flinfo' command. E.g: Bank # 1: CFI conformant flash (16 x 16) Size: 64 MB in 512 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301 Advanced Sector Protection (PPB) enabled Erase timeout: 16384 ms, write timeout: 2 ms Buffer write timeout: 5 ms, buffer size: 32 bytes Sector Start Addresses: FC000000 E FC020000 E RO FC040000 E FC060000 E FC080000 E ... Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Enable PPB protection for all AMD cmdset flash chipsStefan Roese2013-01-10-8/+5
| | | | | | | | | | | | | | | Not only Spansion supports the Persistent Protection Bits (PPB) locking. Other devices like the Micron JS28F512M29EWx also support this type of locking/unlocking. Detection of support is done in the same way as done for the Spansion chips - via the 0x49 CFI word. This patch enables this PPB protection mechanism for all AMD type (AMD commandset) chips. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Read PPB sector protection from device for AMD/Spansion chipsStefan Roese2013-01-10-0/+21
| | | | | | | | | | | | | | | | Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector protection] introduced the PPB (Persistent Protection Bit) locking for Spansion chips. But right now the sector protection status (locked vs unlocked) is set to unlocked for all sectors upon bootup. The real sector protection status is ignored. This patch now reads the current sector protection status and uses it for these AMD/Spansion flash chips. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Holger Brunck <holger.brunck@keymile.com> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* cfi_flash: Add manufact_match helper functionStefan Roese2013-01-10-7/+9
| | | | | | | | Consolidate manufacturer matching into the function manufact_match() and use it. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Holger Brunck <holger.brunck@keymile.com>
* mtd/cfi: add support for SST 4KB sector granularityAngelo Dureghello2013-01-10-1/+24
| | | | | | | | | | | | | | | | | | | Add support for SST 4KB sector granularity. Many recent SST flashes, i.e. SST39VF3201B and similar of this family are declared CFI-conformant from SST. They support CFI query, but implement 2 different sector sizes in the same memory: a 64KB sector (they call it "block", std AMD erase cmd=0x30), and a 4KB sector (they call it "sector", erase cmd=0x50). Also, CFI query on these chips, reading from address 0x2dh of cfi query struct, detects a number of secotrs for the 4KB granularity (flinfo shows it). For all other aspects, they are CFI compliant, so, as Linux do, i think it's a good idea to handle these chips in the CFI driver, with a fixup to allow 4KB granularity, as should be expected, instead of 64KB. Signed-off-by: Angelo Dureghello <sysamfw@gmail.com> Signed-off-by: Stefan Rose <sr@denx.de>
* Fix SPL build for non-ARM targetsAlbert ARIBAUD2013-01-09-0/+4
| | | | Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-01-08-5/+641
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