| Commit message (Collapse) | Author | Age | Lines |
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We have get the right infomation when we call the set_geometry().
So we replace the hardcode with the proper gpmi_info's values.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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In the mx23/mx28, the DATA0_SIZE/DATAN_SIZE of the BCH's
HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be the real
bytes length of the data chunk 0 and data chunk 1.
But in the mx6q/mx50, the DATA0_SIZE/DATAN_SIZE of the BCH's
HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be multiple of 4 bytes.
this patch fixes the wrong macros.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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If tell the real correcting infomation to the upper layer of
MTD, the torture thread of UBIFS will do the torture test in
a very often frequency. This will eat up all the reservation blocks
of the UBIFS.
So tell the real correcting infomation only when the failure occured,
or the corrected times nearly reached the ECC threshold.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Set 0x500 to the busy_timeout in HW_GPMI_TIMING1.
If we do not set this busy_timeout, the gpmi may become unstable.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Rewrite the code for calculate the ecc strength.
Use the same code as in the gpmi driver.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Use the latest gpmi_reset_block(), and remove the old gpmi_nfc_reset_block().
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Abandon our nand chip database, use the community's database.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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update nand_get_flash_type() to the latest code.
Also add the support of ONFI nand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Remove u-boot build warnings for mx6q.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Nand oobsize is wrong in some nand chips.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Spi nor can't erase 0x200000 size.
There are two issues in this CR.
1. Spi nor can't erase 0x200000 size.
2. Whole chip erase don't work.
The solution will be:
1. Delay more time for WIP check.
2. Use normal erase for whole chip erase.
Signed-off-by: Terry Lv <r65388@freescale.com>
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We're following the following rules:
1. FSL copyright should be added for freescale added and modified files.
2. FSL copyright should go after existing copyrights.
3. For Duplicate FSL copyright, Our copyright will go after that also.
4. FSL copyright should not include personal names as part.
5. For only FSL copyright, "All rights reserved" is not mattered.
Signed-off-by: Terry Lv <r65388@freescale.com>
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So far, it's supposed to be on MX50 RD3 and MX53 SMD
Signed-off-by: Robby Cai <R63905@freescale.com>
(cherry picked from commit 0e3d67cd1a2dc30af80e5119b626d997be254991)
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BBT table can't be found on MX53 board, which is due to
that the BBT table flag has been written to the ECC area
which cause the BBT flag lost.
This patch also fix the BBT version not correct issue.
Signed-off-by: Jason Liu <r64343@freescale.com>
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When the NAND has multi-cs, the chip select other than
cs0 is not handled correctly which will lead to NAND not
function as expected
Signed-off-by: Jason Liu <r64343@freescale.com>
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This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Add nand support for mx50 rdp.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Remove the 2G limitation from NAND driver since currently kernel
can support more than 2GB NAND flash now. This commit will make
NAND driver rescan the whole NAND to create one BBT and store to
the last 4 blocks of the larger than 2GB NAND flash. This commit
will have no effect on the NAND which size is not larger than 2GB.
Signed-off-by: Jason Liu <r64343@freescale.com>
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Support nand basic read/write in MX28 u-boot.
Signed-off-by: Frank Li <frank.li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add MT29F16G08ABACA NAND description
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Remove REG_NFC_ONE_CYCLE calling from mxc_nand
driver.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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Add NAND support for MX53 EVK and ARD.
Need to use kobs-ng to flash U-Boot on MX53 TO1. Because
MX51 TO1 ROM doesn't support bi swap solution and kernel
enable bi swap, Must enable "ignore bad block" option when
flashing U-Boot. The step is as following:
echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin
echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad
Since default configuration stores environment into SD
card and U-Boot uses get_mmc_env_devno (Read SBMR register)
to get MMC/SD slot information, you must insert SD card to
bottom SD slot to get/store environment if you are using NAND
boot on MX53 EVK.
You must config boot dip setting well when doing NAND boot.
For example, if you are using NAND 29F32G080AA NAND chip on
MX53 EVK, you can set boot dips as the following for NAND
boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on.
Other dips are off.
Signed-off-by: Lily Zhang <r58066@freescale.com>
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nand read and write page may fail in some pages.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add gpmi nfc and apbh dma support for mx50.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add dwc_ahsata support.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Preserve NAND bad block indication
Signed-off-by:Jason Liu <r64343@freescale.com>
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1. Remove board specific code in mxc_i2c.c.
2. Remove board specific code in mxc_fec.c.
3. Move imx_spi_nor.h to include/asm-arm.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add CONFIG_MXC_NAND config flag in MX25 platform
Signed-off-by: Jason Liu <r64343@freescale.com>
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Update NAND scan scheme to support new nand type. With this
patch uboot can support new NAND flash on mx25/mx35 board
while compatible with old NAND on old boards.
Signed-off-by: Jason Liu <r64343@freescale.com>
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1. Add imx cspi support for cpld access.
2. Add smc911x ethernet support from cpld.
Signed-off-by: Sammy He <r62914@freescale.com>
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Boot from MMC card failed at detecting NAND. The fix will
1. Set RBB_MODE to 1 and using atomic status command
2. Set FW correctly by adding CONFIG_NAND_FW_8 config
3. Correct the BLS register value
Signed-off-by:Jason Liu <r64343@freescale.com>
(cherry picked from commit 7142651386271c340a6ae061a6e2893695675724)
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Change nand Makefile to use CONFIG_MXC_NAND.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Recovery mode support for Android on mx51.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Support Atmel AT45DB321D SPI NOR flash.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Disable NAND driver interleave mode support
Signed-off-by:Jason Liu <r64343@freescale.com>
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Add support for programming ubifs image on nand flash
Signed-off-by:Jason Liu <r64343@freescale.com>
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BBG2, enable SPI NOR and MMC in one image.
Signed-off-by: Terry Lv <r65388@freescale.com>
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1. Add build option to uboot for different media type
2. fix the spi-nor link error
Signed-off-by:Jason Liu <r64343@freescale.com>
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spi nor boot support for BBG2.
Signed-off-by: Terry Lv <r65388@freescale.com>
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Add nand driver for MX51 uboot
Signed-off-by:Jason Liu <r64343@freescale.com>
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This patch add support on U-Boot to i.MX25 processor.
Signed-off-by: Alan Carvalho de Assis <alan.assis@freescale.com>
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Support i.MX51 TO2.0 3stack board. And enable LAN9217 support.
NAND is not supported in this patch.
Signed-off-by: Fred Fan <r01011@freescale.com>
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Modify and Verfiy MX31 & MX35 3stack according to the changes in V2009.01
Signed-off-by: Fred Fan <r01011@freescale.com>
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1. Change NAND driver Makefile to bulild individual nand driver on i.MX31
and i.MX35.
2. Remove CONFIG_NAND_BOOT to common boot code which supports boot from nand
and nor.
Signed-off-by: Fred Fan <r01011@freescale.com>
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Add nand driver for mx35
Signed-off-by:Jason Liu <r64343@freescale.com>
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Support boot from NAND Flash
Add driver for i.MX31 NFC
Upgate U-Boot to support NAND boot
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
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Fix ECC Correction bug where the byte offset location were double
flipped causing correction routine to toggle the wrong byte location
in the ECC segment. The ndfc_calculate_ecc routine change the order
of getting the ECC code.
/* The NDFC uses Smart Media (SMC) bytes order */
ecc_code[0] = p[2];
ecc_code[1] = p[1];
ecc_code[2] = p[3];
But in the Correction algorithm when calculating the byte offset
location, the s1 is used as the upper part of the address. Which
again reverse the order making the final byte offset address
location incorrect.
byteoffs = (s1 << 0) & 0x80;
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byteoffs |= (s0 >> 4) & 0x08;
The order is change to read it in straight and let the correction
function to revert it to SMC order.
Signed-off-by: Feng Kan <fkan@amcc.com>
Acked-by: Victor Gallardo <vgallardo@amcc.com>
Acked-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Signed-off-by: giulio.benetti@micronovasrl.com
Acked-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Scott Wood <scottwood@freescale.com>
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Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51.
The cfi_flash.c driver cast the flash buffer size to a uchar in
flash_write_cfibuffer(). On some flash parts, (tested on Numonyx
part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to
uchar to enable buffer sizes to be larger.
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
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