summaryrefslogtreecommitdiff
path: root/drivers/mtd
Commit message (Collapse)AuthorAgeLines
* sf: Enable byte program supportJagannadha Sutradharudu Teki2014-12-13-12/+19
| | | | | | | | | | | | | | Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* spi: sf: Support byte program for sst spi flashBin Meng2014-12-13-0/+33
| | | | | | | | | | | | | Currently if SST flash advertises SST_WP flag in the params table the word program command (ADh) with auto address increment will be used for the flash write op. However some SPI controllers do not support the word program command (like the Intel ICH 7), the byte programm command (02h) has to be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* spi: Fix flag collision for SST_WPSimon Glass2014-12-13-1/+1
| | | | | | | | | At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix this so that the table in sf_params.c can be used correctly. Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* sf: Fix look for the fastest read commandJagannadha Sutradharudu Teki2014-12-13-56/+60
| | | | | | | | | | | Few of the spi controllers are only supports array slow read which is quite different behaviour compared to others. So this fix on sf will correctly handle the slow read supported controllers. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* driver/mtd: Fix IFC compilation warningsJaiprakash Singh2014-12-11-1/+1
| | | | | | | 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls102xa: Add NAND boot support for LS1021AQDS boardAlison Wang2014-12-11-0/+10
| | | | | | | | | | | This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mtd: nand: omap_gpmc: Always use ready/busy pinStefan Roese2014-12-04-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions to detect the state of the ready / busy signal is already available but only used in the SPL case. Lets use it always, also for the main U-Boot. As all boards should have this HW connection. Testing on Siemens Draco (am335x) showed a small perfomance gain by using this ready pin to detect the NAND chip state. Here the values tested on Draco with Hynix 4GBit NAND: Without NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.947 seconds, 2947 ticks With NAND ready pin: U-Boot# time nand read 80400000 0 400000 NAND read: device 0 offset 0x0, size 0x400000 4194304 bytes read: OK time: 2.795 seconds, 2795 ticks So an increase of approx. 5%. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Samuel Egli <samuel.egli@siemens.com>
* mtd: nand: s3c: Unify the register definition and namingMarek Vasut2014-11-26-19/+19
| | | | | | | | | | | | | | Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Vladimir Zapolskiy <vz@mleia.com>
* mtd/nand/vf610_nfc: Disable subpage writesSanchayan Maity2014-11-26-0/+3
| | | | | | | | | | | | This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* mtd: denali: set some registers after nand_scan_ident()Masahiro Yamada2014-11-26-0/+11
| | | | | | | | | | | | | | | | | Some but not all of implementations of the Denali NAND controller have hardware circuits to detect the device parameters such as page_size, erase_size, etc. Even on those SoCs with such hardware supported, the hardware is known to detect wrong parameters for some nasty (almost buggy) NAND devices. The device parameters detected during nand_scan_ident() are more trustworthy. This commit sets some hardware registers to mtd->pagesize, mtd->oobsize, etc. in the code between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
* mtd: denali: use CONFIG_SYS_NAND_SELF_INITMasahiro Yamada2014-11-26-40/+93
| | | | | | | | | | | | | | | | Some variants of the Denali NAND controller need some registers set up based on the device information that has been detected during nand_scan_ident(). CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce the difference between this driver and its Linux counterpart because this driver was ported from Linux. Moreover, doc/README.nand recommends to use CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
* nand: reinstate lazy bad block scanningRostislav Lisovy2014-11-26-3/+7
| | | | | | | | | | | | | | | Commit ff94bc40af3481d47546595ba73c136de6af6929 ("mtd, ubi, ubifs: resync with Linux-3.14") accidentally reverted part of the commit 13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde ("NAND: Scan bad blocks lazily."). Reinstate the change as by commit fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea ("nand: reinstate lazy bad block scanning") Signed-off-by: Rostislav Lisovy <lisovy@merica.cz> Acked-by: Heiko Schocher <hs@denx.de>
* Merge git://git.denx.de/u-boot-dmTom Rini2014-11-24-2/+2
|\ | | | | | | | | | | | | Conflicts: drivers/serial/serial-uclass.c Signed-off-by: Tom Rini <trini@ti.com>
| * dm: spi: Use device_bind_driver() instead of our own functionSimon Glass2014-11-22-1/+1
| | | | | | | | | | | | | | | | | | | | The SPI function does the same thing, so we may as well just use the new generic function. The 'cs' parameter was not actually used, so can be dropped. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
| * dm: spi: Correct handling of SPI chip selects in sandboxSimon Glass2014-11-22-1/+1
| | | | | | | | | | | | | | | | | | This code was not updated when the chip select handling was adjusted. Fix it to call the correct function. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Acked-by: Heiko Schocher <hs@denx.de>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-4/+5
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ubiTom Rini2014-11-19-0/+1
|\
| * mtd, cfi, ubi: add missing writebufsize initializationHeiko Schocher2014-11-19-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | ff94bc40af3481d47546595ba73c136de6af6929 "mtd, ubi, ubifs: resync with Linux-3.14" introduced the writebufsize field in struct mtd_info, which is not initialized in the cfi_flash driver, which leads in not working ubi on cfi flashes. Fix it Signed-off-by: Heiko Schocher <hs@denx.de> Reported-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* | mtd: Handle 29LV800BTDirk Eibach2014-11-19-0/+51
|/ | | | | | | | | The device id makes u-boot think that this chip needs cfi_reverse_geometry(), which is not the case. Add it to jedec_flash, so it is handled properly. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
* mtd: atmel_nand: runtime to build gf table for pmeccJosh Wu2014-11-17-1/+78
| | | | | | | | | | | | | | | As in SAMA5D4 SoC, the gf table in ROM code can not be seen. So, when we try to use PMECC, we need to build it when do initialization. Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it is defined we will build gf table runtime. The PMECC use the BCH algorithm, so based on the build_gf_tables() function in lib/bch.c, we can build the Galois Field lookup table. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, mtd, nand, atmel_nand: invert device ready pin logicHeiko Schocher2014-11-17-3/+3
| | | | | | | | | | | device ready pin is signalling that the device is ready on state 1 not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* spl, nand, atmel_nand: add erase one block functionHeiko Schocher2014-11-17-0/+33
| | | | | | | | | | | erase one nand block in spl code. keep it simple, as size matters This is used on the upcoming taurus spl support. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: add missing includeHeiko Schocher2014-11-17-0/+1
| | | | | | | | | | | using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-05-2/+7
|\
| * mtd: nand: mxs: Add ECC geometry for 2048b/112b NANDMarek Vasut2014-10-30-2/+7
| | | | | | | | | | | | | | Add ECC geometry for NAND which has 2048b pagesize and 112b OOB size. This is for example Macronix MX30LF2G28AB chip. Signed-off-by: Marek Vasut <marex@denx.de>
* | omap_gpmc: fix warnigs with W=1Jeroen Hofstee2014-10-25-18/+18
| | | | | | | | | | | | | | | | - make omap_spl_dev_ready static - make omap_reverse_list static, move to under CONFIG_NAND_OMAP_ELM Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> Signed-off-by: Tom Rini <trini@ti.com>
* | cti_flash.c: use __weak when requested for flash_(read|write){8,16,32,64}Jeroen Hofstee2014-10-25-34/+16
| | | | | | | | | | | | | | | | | | | | | | For various reasons (design, errata) boards may need to implement their own versions of these accessors. So in the case of CONFIG_CFI_FLASH_USE_WEAK_ACCESSOR mark the functions as weak. In the normal case mark them as static to allow for better optimization. Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> [trini: Reword commit message] Signed-off-by: Tom Rini <trini@ti.com>
* | arm: marvell: Move arch/kirkwood.h to arch/soc.hStefan Roese2014-10-23-1/+1
| | | | | | | | | | | | | | | | | | This move makes is possible to use this header not only from kirkwood platforms but from all Marvell mvebu platforms. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
* | dm: sf: sandbox: Convert SPI flash driver to driver modelSimon Glass2014-10-22-47/+291
| | | | | | | | | | | | | | Convert sandbox's spi flash emulation driver to use driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: Convert spi_flash_probe() and 'sf probe' to use driver modelSimon Glass2014-10-22-2/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want the SPI flash probing feature to operate as a standard driver. Add a driver for the basic probing feature used by most boards. This will be activated by device_probe() as with any other driver. The 'sf probe' command currently keeps track of the SPI slave that it last used. This doesn't work with driver model, since some other driver or system may have probed the device and have access to it too. On the other hand, if we try to probe a device twice the second probe is a nop with driver model. Fix this by searching for the matching device, removing it, and then probing it again. This should work as expected regardless of other device activity. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: sf: Add a uclass for SPI flashSimon Glass2014-10-22-1/+69
| | | | | | | | | | | | | | | | | | | | | | Add a driver model uclass for SPI flash which supports the common operations (read, write, erase). Since we must keep support for the non-dm interface, some modification of the spi_flash header is required. CONFIG_DM_SPI_FLASH is used to enable driver model for SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | spi: Use error return value in sf_opsSimon Glass2014-10-22-33/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | Adjust spi_flash_probe_slave() to return an error value instead of a pointer so we get the correct error return. Have the caller allocate memory for spi_flash to simplify error handling, and also so that driver model can use its existing allocated memory. Add a spi.h include in the sf_params file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | sf: Tidy up public and private header filesSimon Glass2014-10-22-7/+62
| | | | | | | | | | | | | | | | Since spi_flash.h is supposed to be the public API for SPI flash, move private things to sf_internal.h. Also tidy up a few comment nits. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | dm: Add spi.h header to a few filesSimon Glass2014-10-22-0/+1
|/ | | | | | | | Some files are using SPI functions but not explitly including the SPI header file. Fix this, since driver model needs it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2014-10-11-3/+11
|\
| * mtd: denali: support NAND_CMD_RNDOUT commandMasahiro Yamada2014-10-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The function nand_flash_detect_ext_param_page() requires NAND_CMD_RNDOUT command supported. It is necessary to detect some types of ONFi-compliant devices. Without it, the error message "unsupported command received 0x5" is shown. Let's support this command on the Denali NAND controller driver. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Chin Liang See <clsee@altera.com>
| * mtd: denali: fix NAND_CMD_PARAM commandMasahiro Yamada2014-10-09-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NAND_CMD_PARAM (0xEC) command is not working on the Denali NAND controller driver. Unlike NAND_CMD_READID (0x90), when the NAND_CMD_PARAM command is followed by an address cycle, the target device goes busy. (R/B# is deasserted) Wait until the parameter data are ready. In addition, unnecessary clear_interrupts() should be removed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Chin Liang See <clsee@altera.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-10-07-0/+275
| |\
| * | cfi_flash: don't hide write/erase errorsBaruch Siach2014-10-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Partially revert commit 0d01f66d235118 (CFI: cfi_flash write fix for AMD legacy). flash_full_status_check() used to skip status register parsing when flash_status_check() returns OK. This is wrong since flash_status_check() must return OK for other status bits to be valid. Cc: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge remote-tracking branch 'u-boot-imx/master'Albert ARIBAUD2014-10-08-0/+725
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | The single file conflict below is actually trivial. Conflicts: board/boundary/nitrogen6x/nitrogen6x.c
| * | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-09-22-32/+18
| |\ \
| * | | mtd: nand: add Freescale vf610_nfc driverStefan Agner2014-09-16-0/+725
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* | | | mtd: denali: add Denali NAND driver for SPLMasahiro Yamada2014-10-05-0/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP. This driver requires two CONFIG macros: - CONFIG_SPL_NAND_DENALI Define to enable this driver. - CONFIG_SYS_NAND_BAD_BLOCK_POS Specify bad block mark position in the oob space. Typically 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
* | | | mtd: denali: add Denali controller configs to KconfigMasahiro Yamada2014-10-05-0/+33
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support) introduced some new options, and some of them were documented by commit f9860cf081ef (nand/denali: Document CONFIG symbols). This commit allows users to enable/disable them via Kconfig with more detailed help docs. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
* | | Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-26-76/+38
|\ \ \
| * | | sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-26-76/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-26-15/+14
|\ \ \ \ | |/ / / |/| | |
| * | | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-25-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | nand/denali: Adding Denali NAND driver supportChin Liang See2014-09-25-0/+1673
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the Denali NAND driver support into U-Boot. This driver is leveraged from Linux with commit ID fdbad98dff8007f2b8bee6698b5d25ebba0471c9. For Denali controller 64 variance, you need to declare macro CONFIG_SYS_NAND_DENALI_64BIT. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | mtd: nand: Fix length bug in ioread16_rep() and iowrite16_rep()Stefan Roese2014-09-25-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ioread16_rep() and iowrite16_rep() implementations are U-Boot specific and have been introduced with the Linux MTD v3.14 sync. While introducing these functions, the length for the loop has been miscalculated. The ">> 1" is already present in the caller. So lets remove it in the function. Tested on omap3_ha. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Acked-by: Heiko Schocher <hs@denx.de>
generated by cgit v1.1 at 2024-11-09 15:13:17 +0000