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* driver: Add support of image load for MMC & SPI in SPLPrabhakar Kushwaha2014-04-22-0/+14
| | | | | | | Add support of loading image, binary for MMC and SPI during SPL boot. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/mtd/spi:Read 8KB data chunk during u-boot load in SPLPrabhakar Kushwaha2014-04-22-3/+12
| | | | | | | | | | | | | | SPI driver perform its operation(read/write) on 64KB buffer chunk for data greater than 64KB. This buffer chunk is allocated from system heap. During SPL boot, 768KB of data is read from SPI flash. Here, heap size may not be sufficient enough to full-fill 64KB buffer requirement of SPI driver. So break down u-boot read operation at 8KB of chunk. Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ifc: define nand_spl_load_image() for SPLPrabhakar Kushwaha2014-04-22-13/+0
| | | | | | | nand_spl_load_image() can also be used for non TPL framework. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mtd: delete unused filesMasahiro Yamada2014-04-17-1780/+0
| | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com>
* mtd: spi: Fix page size for S25FL032P,S25FL064PMarek Vasut2014-03-17-1/+15
| | | | | | | | | | | | The commit 6af8dc3ebccb3b1e4b2e479315e49545e7f53150 broke support for S25FL032P and S25FL064P by carelessly removing the code handling special page size for these two SPI NOR flashes and unifying the code under the assumption that Extended JEDEC ID of 0x4d00 always implies 512b page size. Add special case handling for these two SPI NOR flashes. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ops: Squash the malloc+memset comboJagannadha Sutradharudu Teki2014-03-17-2/+6
| | | | | | | Squash the malloc()+memset() combo in favor of calloc(). Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Marek Vasut <marex@denx.de>
* sf: Squash the malloc+memset comboMarek Vasut2014-03-17-2/+1
| | | | | | | Squash the malloc()+memset() combo in favor of calloc(). Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add S25FL128S_256K IDsMarek Vasut2014-03-17-0/+1
| | | | | | | Add IDs for this new chip. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Fix entries for S25FL256S_256K and S25FL512S_256KMarek Vasut2014-03-17-2/+2
| | | | | | | | | Both of these chips have 256kB big sectors, thus the _256K suffix, compared to their _64K counterparts, which have 64kB sectors. Also, they have four times less sectors than their _64K counterparts. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-03-10-0/+208
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| * mtd: nand: atmel: prepare for nand spl boot supportBo Shen2014-03-09-0/+208
| | | | | | | | | | | | | | | | | | Prepare for nand spl boot support. It supports nand software ECC and hardware PMECC. This patch is take <drivers/mtd/nand/nand_spl_simple.c> as reference. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | ppc4xx: Remove 4xx NAND booting supportStefan Roese2014-03-07-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* | mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nandpekon gupta2014-03-04-2/+2
| | | | | | | | | | | | | | | | | | omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers ↵pekon gupta2014-03-04-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into common omap_gpmc.h Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related defines and declarations scattered in SoC platform specific header files like include/asm/arch-xx/cpu.h However, GPMC hardware remains same across all platforms thus this patch merges GPMC data scattered across different arch-xx specific header files into single header file include/asm/arch/omap_gpmc.h Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemespekon gupta2014-03-03-90/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip->ecc.correct() is used for detecting and correcting bit-flips during read operations. In omap-nand driver it implemented as: (a) omap_correct_data(): for h/w based ECC_HAM1 scheme (b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW for ECC_BCH8 scheme using GPMC and software lib/bch.c (c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW for ECC_BCH8 scheme using GPMC and ELM This patch updates (c) - checks for calc_ecc[]==0x00 so that error_correction is not required for known good pages. - adds scalability for other ECC_BCHx scheme by merging following omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch() - fixing logic for bit-flip correction based on error_loc[count] Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemespekon gupta2014-03-03-163/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges multiple chip->calculate API for different ECC schemes omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw() ==> omap_calculate_ecc() - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemespekon gupta2014-03-03-142/+56
|/ | | | | | | | | | | | | | | | | | | chip->ecc.hwctl() is used for preparing the H/W controller before read/write NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.) Though all ECC schemes in OMAP NAND driver use GPMC controller for generating ECC syndrome (for both Read/Write accesses). But but in current code HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this. This patch (1) removes omap_hwecc_init() and omap_hwecc_init_bch() as chip->ecc.hwctl will re-initializeGPMC before every read/write call. omap_hwecc_init_bch() -> omap_enable_ecc_bch() (2) merges the GPMC configuration code for all ECC schemes into single omap_enable_hwecc(), thus adding scalability for future ECC schemes. omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc() Signed-off-by: Pekon Gupta <pekon@ti.com>
* driver/ifc:Change accessor function to take care of endiannessPrabhakar Kushwaha2014-02-03-151/+152
| | | | | | | | | | | IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc:mpc85xx: Add ifc nand boot support for TPL/SPLPo Liu2014-01-21-7/+24
| | | | | | | | | | | | | | | Using the TPL method for nand boot by sram was already supported. Here add some code for mpc85xx ifc nand boot. - For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec. - Use a clear function name for nand spl boot. - Add CONFIG_SPL_DRIVERS_MISC_SUPPORT to compile the fsl_ifc.c in spl/Makefile; Signed-off-by: Po Liu <Po.Liu@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* nand, gpmc: fix reading after switching eccJeroen Hofstee2014-01-17-0/+1
| | | | | | | | | | | | | | The omap_gpmc allows switching ecc at runtime. Since the NAND_SUBPAGE_READ flag is only set, it is kept when switching to hw ecc, which is not correct. This leads to calling chip->ecc.read_subpage which is not a valid pointer. Therefore clear the flag when switching ecc so reading in hw mode works again. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
* sf: params: Removed flag SECT_4K for Micron N25Q128Siva Durga Prasad Paladugu2014-01-12-2/+2
| | | | | | | | | Remove the flag SECT_4K for device N25Q128 as the 4K-byte sub sector erase granularity is available only for top/bottom 8 sectors in some of the N25Q128 chips. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add CONFIG_SF_DUAL_FLASHJagannadha Sutradharudu Teki2014-01-12-5/+14
| | | | | | | This config will use for defining greater than single flash support. currently - DUAL_STACKED and DUAL_PARALLEL. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add dual memories support - DUAL_PARALLELJagannadha Sutradharudu Teki2014-01-12-7/+12
| | | | | | | | | This patch added support for accessing dual memories in parallel connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add dual memories support - DUAL_STACKEDJagannadha Sutradharudu Teki2014-01-12-11/+57
| | | | | | | | | This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ops: Unify read_ops bank configurationJagannadha Sutradharudu Teki2014-01-12-8/+5
| | | | | | Unified the bar code from read_ops into a spi_flash_bar() Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Code cleanupsJagannadha Sutradharudu Teki2014-01-12-13/+8
| | | | | | | - comment typo's - func args have a proper names Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Divide flash register ops from QEB codeJagannadha Sutradharudu Teki2014-01-11-53/+77
| | | | | | | QEB code comprises of couple of flash register read/write operations, this patch moved flash register operations on to sf_op Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Enable macronix quad read/write cmds supportJagannadha Sutradharudu Teki2014-01-11-4/+4
| | | | | | | | | Added macronix flash quad read/write commands support and it's up to the respective controller driver usecase to configure the respective commands by defining SPI RX/TX operation modes from include/spi.h on the driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add macronix set QEB supportJagannadha Sutradharudu Teki2014-01-11-0/+35
| | | | | | | This patch adds set QEB support for macronix flash devices which are trying to program/read quad operations. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Discover read dummy_byteJagannadha Sutradharudu Teki2014-01-11-7/+30
| | | | | | | Discovered the read dummy_byte based on the configured read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add QUAD_IO_FAST read supportJagannadha Sutradharudu Teki2014-01-11-0/+3
| | | | | | This patch adds support QUAD_IO_FAST read command. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Separate the flash params tableJagannadha Sutradharudu Teki2014-01-11-145/+135
| | | | | | | | Moved the flash params table from sf_probe.c and placed on to sf_params.c, hence flash params file will alter based on new addons. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: probe: Enable RD_FULL and WR_QPPJagannadha Sutradharudu Teki2014-01-11-30/+30
| | | | | | | | | This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Set quad enable bit supportJagannadha Sutradharudu Teki2014-01-11-2/+62
| | | | | | | | | | | | | This patch provides support to set the quad enable bit on flash. quad enable bit needs to set before performing any quad IO operations on respective SPI flashes. Currently added set quad enable bit for winbond and spansion flash devices. stmicro flash doesn't require to set as qeb is volatile. remaining flash devices support will add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: ops: Add configuration register writing supportJagannadha Sutradharudu Teki2014-01-11-0/+24
| | | | | | | | | This patch provides support to program a flash config register. Configuration register contains the control bits used to configure the different configurations and security features of a device. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add quad read/write commands supportJagannadha Sutradharudu Teki2014-01-11-86/+96
| | | | | | | | This patch add quad commands support like - QUAD_PAGE_PROGRAM => for write program - QUAD_OUTPUT_FAST ->> for read program Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* sf: Add extended read commands supportJagannadha Sutradharudu Teki2014-01-11-86/+108
| | | | | | | | | | | Current sf uses FAST_READ command, this patch adds support to use the different/extended read command. This implementation will determine the fastest command by taking the supported commands from the flash and the controller, controller is always been a priority. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
* mtd: onenand: Fix unaligned accessMarek Vasut2013-12-31-1/+7
| | | | | | | | | | | | | | | Fix unaligned access in OneNAND core. The problem is that the ffchars[] array is an array of "unsigned char", but in onenand_write_ops_nolock() can be passed to the memcpy_16() function. The memcpy_16() function will treat the buffer as an array of "unsigned short", thus triggering unaligned access if the compiler decided ffchars[] to be not aligned. I managed to trigger the problem with regular ELDK 5.4 GCC compiler. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2013-12-19-1/+8
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| * driver: mtd: sf_ops: claim bus while doing memcpyPoddar, Sourav2013-12-19-0/+6
| | | | | | | | | | | | | | | | | | | | claim spi bus while doing memory copy, this will set up the spi controller device control register before doing a memory read. Signed-off-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Yebio Mesfin <ymesfin@ti.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * sf: probe: add support for MX25L2006ELuka Perkov2013-12-18-0/+1
| | | | | | | | | | | | | | Add support for Macronix MX25L2006E SPI flash. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * sf: probe: Hex values are in lower caseLuka Perkov2013-12-18-1/+1
| | | | | | | | | | | | | | | | All other hex values in sf_probe.c are in lower case so we should fix this one too. Signed-off-by: Luka Perkov <luka@openwrt.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
* | mtd: nand: omap: fix ecc ops assignment when changing eccNikita Kiryanov2013-12-17-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we change to software ecc and then back to hardware ecc, the nand ecc ops pointers are populated with incorrect function pointers. This is related to the way nand_scan_tail() handles assigning functions to ecc ops: If we are switching to software ecc/no ecc, it assigns default functions to the ecc ops pointers unconditionally, but if we are switching to hardware ecc, the default hardware ecc functions are assigned to ops pointers only if these pointers are NULL (so that drivers could set their own functions). In the case of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc, the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite them with hw ecc functions. The result: sw ecc functions used to write hw ecc data. Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that ops which were not assigned by the driver will get the correct default values from nand_scan_tail(). Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | mtd: nand: omap: fix sw->hw->sw ecc switchNikita Kiryanov2013-12-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate values into the current nand chip's ecc.layout struct. This is done under the assumption that the struct exists only to store values, so it is OK to overwrite it, but there is at least one situation where this assumption is incorrect: When switching to 1 bit hamming code sw ecc, the job of assigning layout data is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a pointer to an existing struct prefilled with the appropriate values. This struct doubles as both data and layout definition, and therefore shouldn't be overwritten, but on the next switch to hardware ecc, this is exactly what's going to happen. The next time the user switches to software ecc, they're going to get a messed up ecc layout. Prevent this and possible similar bugs by explicitly using the private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode. Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | nand_util.c: Use '%zd' for length in nand_unlock debug printTom Rini2013-12-17-1/+1
| | | | | | | | | | | | | | length is size_t so needs to be '%zd' not '%d' to avoid warnings. Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
* | mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.sizeNikita Kiryanov2013-12-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "mtd: nand: omap: enable BCH ECC scheme using ELM for generic platform" (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way software ECC is configured, both during boot, and during ecc switch, in a way that is not backwards compatible with older systems: Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring for software ecc, relying on nand_scan_tail() to select a default for ecc.size (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize, which is likely to not be 256. Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert to the original behavior. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Pekon Gupta <pekon@ti.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Pekon Gupta <pekon@ti.com>
* | mtd: nand: omap_gpmc: cosmetic: Fix indentationStefan Roese2013-12-17-43/+45
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Scott Wood <scottwood@freescale.com> [scottwood@freescale.com: wrap some long lines] Signed-off-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand: omap: fix ecc-layout for HAM1 ecc-schemepekon gupta2013-12-17-2/+6
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per OMAP3530 TRM referenced below [1] For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is: *for x8 NAND Device* +--------+---------+---------+---------+---------+---------+---------+ | xxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ... +--------+---------+---------+---------+---------+---------+---------+ *for x16 NAND Device* +--------+--------+---------+---------+---------+---------+---------+---------+ | xxxxx | xxxxx | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | +--------+--------+---------+---------+---------+---------+---------+---------+ This patch fixes ecc-layout *only* for HAM1, as required by ROM-code For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices. [1] OMAP3530: http://www.ti.com/product/omap3530 TRM: http://www.ti.com/litv/pdf/spruf98x Chapter-25: Initialization Sub-topic: Memory Booting Section: 25.4.7.4 NAND Figure 25-19. ECC Locations in NAND Spare Areas Reported-by: Stefan Roese <sr@denx.de> Signed-off-by: Pekon Gupta <pekon@ti.com> Tested-by: Stefan Roese <sr@denx.de>
* drivers/mtd: descend into sub directories only when it is necessaryMasahiro Yamada2013-12-13-6/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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