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* ENGR00231581 BCH: fix the wrong data size macros in BCHHuang Shijie2012-10-30-3/+8
| | | | | | | | | | | | | In the mx23/mx28, the DATA0_SIZE/DATAN_SIZE of the BCH's HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be the real bytes length of the data chunk 0 and data chunk 1. But in the mx6q/mx50, the DATA0_SIZE/DATAN_SIZE of the BCH's HW_BCH_FLASH1LAYOUT0/HW_BCH_FLASH0LAYOUT1 should be multiple of 4 bytes. this patch fixes the wrong macros. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-7 uboot: gpmi: update the mtd->ecc_stats when reading page failedHuang Shijie2012-08-20-3/+8
| | | | | | | | | | | | If tell the real correcting infomation to the upper layer of MTD, the torture thread of UBIFS will do the torture test in a very often frequency. This will eat up all the reservation blocks of the UBIFS. So tell the real correcting infomation only when the failure occured, or the corrected times nearly reached the ECC threshold. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-6 uboot: gpmi: set default value for busy_timeoutHuang Shijie2012-08-20-0/+5
| | | | | | | Set 0x500 to the busy_timeout in HW_GPMI_TIMING1. If we do not set this busy_timeout, the gpmi may become unstable. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-5 uboot: gpmi: update the ecc_strength codeHuang Shijie2012-08-20-66/+160
| | | | | | | Rewrite the code for calculate the ecc strength. Use the same code as in the gpmi driver. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-4 uboot: gpmi: replace the gpmi_nfc_reset_block()Huang Shijie2012-08-20-77/+96
| | | | | | Use the latest gpmi_reset_block(), and remove the old gpmi_nfc_reset_block(). Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-3 uboot: gpmi: use the community's nand chip databaseHuang Shijie2012-08-20-108/+19
| | | | | | Abandon our nand chip database, use the community's database. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00217505-2 uboot: mtd: update nand_get_flash_type()Huang Shijie2012-08-20-33/+257
| | | | | | | update nand_get_flash_type() to the latest code. Also add the support of ONFI nand. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00161852: remove u-boot build warnings for mx6qTerry Lv2011-11-10-0/+2
| | | | | | Remove u-boot build warnings for mx6q. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143704: U_BOOT: Nand oobsize is wrong in some nand chipsTerry Lv2011-05-20-7/+11
| | | | | | Nand oobsize is wrong in some nand chips. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-13/+13
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-2/+4
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140486 Add SPI NOR Flash M25P32 driverRobby Cai2011-03-18-0/+549
| | | | | | | So far, it's supposed to be on MX50 RD3 and MX53 SMD Signed-off-by: Robby Cai <R63905@freescale.com> (cherry picked from commit 0e3d67cd1a2dc30af80e5119b626d997be254991)
* ENGR00137390 UBOOT:NAND: BBT not found on MX53 boardJason Liu2010-12-27-0/+7
| | | | | | | | | | BBT table can't be found on MX53 board, which is due to that the BBT table flag has been written to the ECC area which cause the BBT flag lost. This patch also fix the BBT version not correct issue. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00134220-1 NAND: fix up the chip select handlingJason Liu2010-12-07-10/+16
| | | | | | | | When the NAND has multi-cs, the chip select other than cs0 is not handled correctly which will lead to NAND not function as expected Signed-off-by: Jason Liu <r64343@freescale.com>
* NAND: Update to support 64 bit device sizeSandeep Paulraj2010-12-03-28/+39
| | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ENGR00133124: Add nand support for mx50 rdpTerry Lv2010-11-18-15/+8
| | | | | | Add nand support for mx50 rdp. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00133756:UBOOT:NAND:Remove the 2G limitation from NAND driverJason Liu2010-11-16-10/+0
| | | | | | | | | | Remove the 2G limitation from NAND driver since currently kernel can support more than 2GB NAND flash now. This commit will make NAND driver rescan the whole NAND to create one BBT and store to the last 4 blocks of the larger than 2GB NAND flash. This commit will have no effect on the NAND which size is not larger than 2GB. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00133049 Support nand flash for MX28Frank Li2010-11-04-5/+5
| | | | | | | Support nand basic read/write in MX28 u-boot. Signed-off-by: Frank Li <frank.li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00132965 add MT29F16G08ABACA NAND descriptionLily Zhang2010-10-26-0/+5
| | | | | | Add MT29F16G08ABACA NAND description Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132727 NAND: remove REG_NFC_ONE_CYCLE callingLily Zhang2010-10-18-2/+0
| | | | | | | Remove REG_NFC_ONE_CYCLE calling from mxc_nand driver. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132617 MX53: add NAND supportLily Zhang2010-10-17-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for MX53 EVK and ARD. Need to use kobs-ng to flash U-Boot on MX53 TO1. Because MX51 TO1 ROM doesn't support bi swap solution and kernel enable bi swap, Must enable "ignore bad block" option when flashing U-Boot. The step is as following: echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad Since default configuration stores environment into SD card and U-Boot uses get_mmc_env_devno (Read SBMR register) to get MMC/SD slot information, you must insert SD card to bottom SD slot to get/store environment if you are using NAND boot on MX53 EVK. You must config boot dip setting well when doing NAND boot. For example, if you are using NAND 29F32G080AA NAND chip on MX53 EVK, you can set boot dips as the following for NAND boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on. Other dips are off. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132014: nand read and write page may fail in some pagesTerry Lv2010-09-28-30/+33
| | | | | | nand read and write page may fail in some pages. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00127167: Add gpmi nfc and apbh dma support for mx50.Terry Lv2010-09-19-0/+4591
| | | | | | Add gpmi nfc and apbh dma support for mx50. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00122651: Add dwc_ahsata supportTerry Lv2010-06-24-1/+2
| | | | | | Add dwc_ahsata support. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00123265 UBOOT:Preserve NAND bad block indicationJason Liu2010-05-07-1/+29
| | | | | | Preserve NAND bad block indication Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00121832: Some code reconstructure for u-bootTerry Lv2010-03-22-4/+4
| | | | | | | | 1. Remove board specific code in mxc_i2c.c. 2. Remove board specific code in mxc_fec.c. 3. Move imx_spi_nor.h to include/asm-arm. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00119246 Add CONFIG_MXC_NAND config flag in MX25 platformJason2009-12-11-1/+0
| | | | | | Add CONFIG_MXC_NAND config flag in MX25 platform Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00118789 Uboot:Update NAND scan scheme to support new nand typeJason2009-12-08-4/+2493
| | | | | | | | Update NAND scan scheme to support new nand type. With this patch uboot can support new NAND flash on mx25/mx35 board while compatible with old NAND on old boards. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00118576 MX25: Support Smc911x ethernetSammy He2009-11-20-2/+2
| | | | | | | 1. Add imx cspi support for cpld access. 2. Add smc911x ethernet support from cpld. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00116924 Uboot: Boot up hang at detecting NAND when cold bootJason2009-11-04-14/+45
| | | | | | | | | | Boot from MMC card failed at detecting NAND. The fix will 1. Set RBB_MODE to 1 and using atomic status command 2. Set FW correctly by adding CONFIG_NAND_FW_8 config 3. Correct the BLS register value Signed-off-by:Jason Liu <r64343@freescale.com> (cherry picked from commit 7142651386271c340a6ae061a6e2893695675724)
* ENGR00116203: Change nand Makefile to use CONFIG_MXC_NAND.Terry Lv2009-09-10-2/+1
| | | | | | Change nand Makefile to use CONFIG_MXC_NAND. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00116083: Recovery mode support for Android on mx51.Terry Lv2009-09-10-1/+1
| | | | | | Recovery mode support for Android on mx51. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00114393: Support Atmel AT45DB321D SPI NOR flash.Terry Lv2009-09-10-0/+533
| | | | | | Support Atmel AT45DB321D SPI NOR flash. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00114236 Disable NAND driver interleave mode supportJason2009-09-10-23/+13
| | | | | | Disable NAND driver interleave mode support Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00114233 Add support for programming ubifs image on nand flashJason2009-09-10-0/+67
| | | | | | Add support for programming ubifs image on nand flash Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00113439: BBG2, enable SPI NOR and MMC in one image.Terry Lv2009-09-10-5/+11
| | | | | | BBG2, enable SPI NOR and MMC in one image. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00113148 Add build option to uboot for different media typeJason2009-09-10-1/+1
| | | | | | | 1. Add build option to uboot for different media type 2. fix the spi-nor link error Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00112845 spi nor boot and pmic support for BBG2.Terry Lv2009-09-10-0/+560
| | | | | | spi nor boot support for BBG2. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00109851 Add nand driver for MX51 ubootJason2009-09-10-212/+257
| | | | | | Add nand driver for MX51 uboot Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00108673 Add i.MX25 core to U-BootAlan Carvalho de Assis2009-09-10-0/+1
| | | | | | This patch add support on U-Boot to i.MX25 processor. Signed-off-by: Alan Carvalho de Assis <alan.assis@freescale.com>
* ENGR00108473 Porting i.MX51 3stack TO2 support to V2009.01Fred Fan2009-09-10-0/+1
| | | | | | | Support i.MX51 TO2.0 3stack board. And enable LAN9217 support. NAND is not supported in this patch. Signed-off-by: Fred Fan <r01011@freescale.com>
* ENGR00107886 Porting MX31, MX35 3stack to u-boot V2009.01Fred Fan2009-09-10-93/+88
| | | | | | Modify and Verfiy MX31 & MX35 3stack according to the changes in V2009.01 Signed-off-by: Fred Fan <r01011@freescale.com>
* ENGR00102788 Remove CONFIG_NAND_BOOT on i.MX31 3stackFred Fan2009-09-09-1/+1
| | | | | | | | | 1. Change NAND driver Makefile to bulild individual nand driver on i.MX31 and i.MX35. 2. Remove CONFIG_NAND_BOOT to common boot code which supports boot from nand and nor. Signed-off-by: Fred Fan <r01011@freescale.com>
* ENGR00099697 Add nand driver for mx35Fred Fan2009-09-09-12/+1158
| | | | | | Add nand driver for mx35 Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00094619 Support i.MX31 3stack boardFred Fan2009-09-09-0/+970
| | | | | | | | Support boot from NAND Flash Add driver for i.MX31 NFC Upgate U-Boot to support NAND boot Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
* ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driverFeng Kan2009-08-25-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by: Feng Kan <fkan@amcc.com> Acked-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* eeprom_m95xxx: remove unused variable iJean-Christophe PLAGNIOL-VILLARD2009-08-21-1/+0
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* add WATCHDOG_RESET() on nand write and readGiulio Benetti2009-08-21-0/+4
| | | | | | Signed-off-by: giulio.benetti@micronovasrl.com Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
* flash: Fix CFI buffer size bugJohn Schmoller2009-08-13-1/+1
| | | | | | | | | | | | Fix bug introduced by 9c048b523413ae5f3ff34e00cf57569c3368ab51. The cfi_flash.c driver cast the flash buffer size to a uchar in flash_write_cfibuffer(). On some flash parts, (tested on Numonyx part PC32F512M29EWH), the buffer size is 1KB. Remove the cast to uchar to enable buffer sizes to be larger. Signed-off-by: John Schmoller <jschmoller@xes-inc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Add driver for the ST M95xxx SPI EEPROMAlbin Tonnerre2009-08-09-0/+118
| | | | | | | | This chip is used in a number of boards manufactured by Calao-Systems which should be supported soon. This driver provides the necessary spi_read and spi_write functions necessary to communicate with the chip. Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
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