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* fsl_elbc_nand: redirect the pointer of bbt pattern to RAMMingkai Hu2009-07-07-0/+4
| | | | | | | | | | | The bbt descriptors contains the pointer to the bbt pattern which are statically initialized memory struct. When relocated to RAM, these pointers will continue point to NOR flash(or L2 SRAM, or other boot device). If the contents of NOR flash changed or L2 SRAM disabled, it'll hang the system. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Bug-fix in drivers mtd nand Makefilekevin.morfitt@fearnside-systems.co.uk2009-07-07-1/+1
| | | | | | | | The S3C2410 NAND driver source file is included in the makefile instead of the object file. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: nand: use loff_t for offsetJean-Christophe PLAGNIOL-VILLARD2009-07-07-10/+10
| | | | | | | | nand_util currently uses size_t which is arch dependent and not always a unsigned long. Now use loff_t, as does the linux mtd layer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: nand: new base driver for memory mapped nand devicesMike Frysinger2009-07-07-0/+54
| | | | | | | | | The BF537-STAMP Blackfin board had a driver for working with NAND devices that are simply memory mapped. Since there is nothing Blackfin specific about this, generalize the driver a bit so that everyone can leverage it. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand chipselect/init cleanupDavid Brownell2009-07-07-20/+8
| | | | | | | | | | | | | | | | | Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)David Brownell2009-07-07-205/+13
| | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand: cleanup I (minor)David Brownell2009-07-07-33/+22
| | | | | | | | | | | | | | | | | | | | | | | | Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ARM DaVinci: EMIF settingsThomas Lange2009-07-06-9/+3
| | | | | | | | | | | NAND module should not modify EMIF registers unrelated to CS2 that is used for NAND, i.e. do not modify EWAIT config register or registers for other Chip Selects. Without this patch, EMIF configurations made in board_init() will be invalidated. Signed-off-by: Thomas Lange <thomas@corelatus.se>
* nand/mpc512x: Add MPC512x NAND support (NFC)Stefan Roese2009-06-12-0/+693
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds NAND Flash Controller driver for MPC5121 revision 2. All device features, except hardware ECC and power management, are supported. This NFC driver replaces the one orignally posted by John Rigby: "[PATCH] Freescale NFC NAND driver" It's a port of the Linux driver version posted by Piotr Ziecik a few weeks ago. Using this driver has the following advantages (from my point of view): - Compatibility with the Linux NAND driver (e.g. ECC usage) - Better code quality in general - Resulting U-Boot image is a bit smaller (approx. 3k) - Better to sync with newer Linux driver versions The only disadvantage I can see, is that HW-ECC is not supported right now. But this could be added later (e.g. port from Linux driver after it's supported there). Using HW-ECC on the MCP5121 NFC has a general problem because of the ECC usage in the spare area. This collides with JFFS2 for example. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Piotr Ziecik <kosmo@semihalf.com> Cc: Wolfgang Denk <wd@denx.de> Cc: John Rigby <jcrigby@gmail.com> Cc: Scott Wood <scottwood@freescale.com>
* mtd: Introduce CONFIG_MTD_DEVICE to select compilation of mtdcore.oStefan Roese2009-06-12-1/+1
| | | | | | | | | | | | | This new define enables mtdcore.c compilation and with this we can select the MTD device infrastructure needed for the reworked mtdparts command. We now have the 2 MTD infrastructure defines, CONFIG_MTD_DEVICE and CONFIG_MTD_PARTITIONS. CONFIG_MTD_DEVICE is needed (as explained above) for the "mtdparts" command and CONFIG_MTD_PARTITIONS is needed for UBI. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com>
* mtd: Update MTD infrastructure to support 64bit device sizeStefan Roese2009-06-12-4/+7
| | | | | | | | | | | This patch brings the U-Boot MTD infrastructure in sync with the current Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size support and a resync of the mtdpart.c file which has seen multiple fixes meanwhile. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Kyungmin Park <kmpark@infradead.org>
* nand: Fix problem with ECC ordering for PPC4xx NDFC platformsStefan Roese2009-05-23-0/+5
| | | | | | | | | This patch enables Smart Media (SMC) ECC byte ordering which is used on the PPC4xx NAND FLASH controller (NDFC). Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* mtd: nand/onenand: Register mtd device upon device scanningStefan Roese2009-04-28-0/+12
| | | | | | | | | With this patch the NAND and OneNAND devices are registered in the MTD subsystem and can then be referenced by the mtdcore code (e.g. get_mtd_device_nm()). This is needed for the new "ubi part" command syntax without the flash type parameter (nor|nand|onenand). Signed-off-by: Stefan Roese <sr@denx.de>
* mtd: nand: Include linux/mtd/partitions.h in nand_base.hStefan Roese2009-04-28-0/+4
| | | | | | | | | | This patch removes this compilation warning when CONFIG_MTD_PARTITIONS is defined: nand_base.c: In function 'nand_release': nand_base.c:2922: warning: implicit declaration of function 'del_mtd_partitions' Signed-off-by: Stefan Roese <sr@denx.de>
* Blackfin: nand: flush peripheral before polling itGraf Yang2009-04-06-0/+1
| | | | | | | | | | We need to make sure the data written to the nand flash controller makes it there before we start polling its status register. Otherwise, we may get stale data and return before the controller is actually ready. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Scott Wood <scottwood@freescale.com>
* s3c2410: move nand driver to drivers/mtd/nandJean-Christophe PLAGNIOL-VILLARD2009-03-30-0/+172
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* davinci: move nand driver to drivers/mtd/nandJean-Christophe PLAGNIOL-VILLARD2009-03-30-0/+467
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://git.denx.de/u-boot-at91Wolfgang Denk2009-03-26-0/+79
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| * at91sam9/at91cap: move nand drivers to drivers/mtd/nandJean-Christophe PLAGNIOL-VILLARD2009-03-22-0/+79
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Add wait flags to support board/chip specific delaysWolfgang Grandegger2009-03-23-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND flash on the TQM8548_BE modules requires a short delay after running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE requires a further short delay after writing out a buffer. Normally the R/B pin should be checked, but it's not connected on the TQM8548_BE. The corresponding Linux FSL UPM driver uses similar delay points at the same locations. To manage these extra delays in a more general way, I introduced the "wait_flags" field allowing the board-specific driver to specify various types of extra delay. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add support for TQM-specific chip select logic to FSL-UPMWolfgang Grandegger2009-03-23-1/+4
| | | | | | | | | | | | | | | | | | For the NAND chips on the TQM8548 modules, a special chip-select logic is used. It uses dedicated address lines to be set via UPM machine address register (mar). This patch adds such support to the FSL-UPM driver. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Add multi chip support to the FSL-UPM driverWolfgang Grandegger2009-03-23-8/+36
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for multi-chip NAND devices to the FSL-UPM driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now called with the argument "chip_nr" to allow testing the proper chip select line. The NAND support of the MPC8360ERDK is updated as well. No other boards are currently using the FSL UPM driver. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Enable multi chip support in the NAND layerWolfgang Grandegger2009-03-23-1/+7
|/ | | | | | | | | | This patch adds support for NAND_MAX_CHIPS to the MTD NAND layer. Multi-chips devices are displayed as shown: Device 0: 2x NAND 512MiB 3,3V 8-bit, sector size 128 KiB Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* nomadik/nand: fix 'ecc512' discards qualifiers from pointer target typeJean-Christophe PLAGNIOL-VILLARD2009-02-22-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Nand driver for Nomadik SoCAlessandro Rubini2009-02-22-0/+222
| | | | | | | | | | This driver implements the ECC algorithm described in the CPU data sheet and uses the OOB layout chosen in already-released development systems (shipped with a custom-made u-boot 1.3.1). Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com>
* NAND: Add timeout for reset commandPeter Tyser2009-02-06-2/+17
| | | | | | | | Without the timeout present an infinite loop can occur if the NAND device is broken or not present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Silence warning when CONFIG_SYS_NAND_QUIET_TESTPeter Tyser2009-02-06-0/+2
| | | | | | | | | | Commit cfa460adfdefcc30d104e1a9ee44994ee349bb7b removed support for disabling the "No NAND device found!!!" warning when CONFIG_SYS_NAND_QUIET_TEST was defined. This re-adds support for silencing the warning. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Fixed invalid pointers to static relocated chip namesValeriy Glushkov2009-02-06-0/+4
| | | | | | | | | | Dear Wolfgang, You are right, the patch was ugly. The new one seems to be better. Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Blackfin: add driver for on-chip NAND controllerMike Frysinger2009-02-02-0/+386
| | | | | | This is a port of the Linux Blackfin on-chip NFC driver to U-Boot. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* OMAP3: Add NAND supportDirk Behme2009-01-24-0/+354
| | | | | | | | Add NAND support. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Syed Mohammed Khasim <khasim@ti.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* nand: fixup printf modifiers to match types usedMike Frysinger2009-01-23-6/+6
| | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: rename NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPSWolfgang Grandegger2009-01-23-1/+1
| | | | | | | | | | | | | | | | This patch renames NAND_MAX_CHIPS to CONFIG_SYS_NAND_MAX_CHIPS and changes the default from 8 to 1 for the legacy and the new MTD NAND layer. This allows to remove all NAND_MAX_CHIPS definitions in the board config files because none of the boards use multi chip support (NAND_MAX_CHIPS > 1) so far. The bamboo and the DU440 define #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE but that's bogus and did not work anyhow. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Enable nand lock, unlock featureNishanth Menon2009-01-23-36/+43
| | | | | | | | | | | | | | | | Enable nand lock, unlock and status of lock feature. Not every device and platform requires this, hence, it is under define for CONFIG_CMD_NAND_LOCK_UNLOCK Nand unlock and status operate on block boundary instead of page boundary. Details in: http://www.micron.com/products/partdetail?part=MT29C2G24MAKLAJG-6%20IT Intial solution provided by Vikram Pandita <vikram.pandita@ti.com> Includes preliminary suggestions from Scott Wood Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: move board_nand_init to nand.hMike Frysinger2009-01-23-2/+0
| | | | | | | | | | | Rather than putting the function prototype for board_nand_init() in the one place where it gets called, put it into nand.h so that every place that also defines it gets the prototype. Otherwise, errors can go silently unnoticed such as using the wrong return value (void rather than int) when defining the function. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-12-30-2/+4
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| * NAND FSL elbc: Use virt_to_phys to determine which bank is in useKumar Gala2008-12-19-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | The current code that determines which bank/chipselect is used for a given NAND instance only worked for 32-bit addresses and assumed a 1:1 mapping. This breaks in 36-bit physical configs. The proper way to handle this is to use the virt_to_phys() and BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address with the the virtual address the NAND code uses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Scott Wood <scottwood@freescale.com>
* | NAND: Mark the BBT as scanned prior to calling scan_bbt.Scott Wood2008-12-16-1/+1
|/ | | | | | | | Otherwise, recursion can occur if scan_bbt does not find a bad block table, and tries to write one, and the attempt to erase the BBT area causes a bad block check. Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Fix misplaced return statement in nand_{read,write}_skip_bad().Scott Wood2008-11-25-6/+6
| | | | | | | | This caused the operation to be needlessly repeated if there were no bad blocks and no errors. Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Properly create JFFS2 cleanmarkers.Scott Wood2008-10-29-19/+11
| | | | | | | | | | | As reported by Ilko Iliev <iliev@ronetix.at>, the "nand erase clean" command is currently broken, and among other things causes all blocks to be marked bad. This implements it properly using MTD_OOB_AUTO, along with some indentation fixes. Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND fsl elbc: Set FMR[ECCM] based on page size.Scott Wood2008-10-29-2/+14
| | | | | | | Hardware expects ECCM 0 for small page and ECCM 1 for large page when booting from NAND, so use those defaults. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-9/+11
| | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: Reset chip on power-upKarl Beldan2008-10-29-0/+8
| | | | | | | | | | Some chips require a RESET after power-up (e.g. Micron MT29FxGxxxxx). The first command sent is NAND_CMD_READID. Issue a NAND_CMD_RESET in nand_scan_ident before reading the device id. Tested with an MT29F4G08AAC. Signed-off-by: Karl Beldan <karl.beldan@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: sync with 2.6.27Scott Wood2008-10-29-42/+140
| | | | | | | | | | | | | This brings the core NAND code up to date with the Linux kernel. Since there were several drivers in Linux as of the last update that are not in u-boot, I'm not bringing over new drivers that have been added since in the absence of an interested party. I did not update OneNAND since it was recently synced by Kyungmin Park, and I'm not sure exactly what the common ancestor is. Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-17/+17
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Fix the NAND size overflow issue.Jason Jin2008-10-14-2/+2
| | | | | | | | | | | | | When the total size of all NAND devices exceeds 4 GiB, the size will overflow. This patch tries to fix this. Note that we still have a problem when a single NAND device is bigger than 4 GiB: then the overflow would actually happen earlier, i. e. when storing the size in nand_info[].size, as nand_info[].size is an "u_int32_t". Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* fsl_elbc_nand: ecclayout cleanupsAnton Vorontsov2008-09-12-4/+0
| | | | | | | | | | This patch deletes oobavail assignments, they're calculated by the nand core code in nand_scan_tail, plus current oobavail values are wrong for the LP NANDs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: implement support for flash-based BBTAnton Vorontsov2008-09-12-1/+34
| | | | | | | | | | | | | This patch implements support for flash-based BBT for chips working through ELBC NAND controller, so that NAND core will not have to re-scan for bad blocks on every boot. Because ELBC controller may provide HW-generated ECCs we should adjust bbt pattern and bbt version positions in the OOB free area. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: fix OOB workability for large page NAND chipsAnton Vorontsov2008-09-12-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For large page chips, nand_bbt is looking into OOB area, and checking for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be reserved for bbt means. But ELBC driver is specifying ecclayout so that oobfree area starts at offset 1, so only one byte left for the bbt purposes. This causes problems with any OOB users, namely JFFS2: after first mount JFFS2 will fill all OOBs with "erased marker", so OOBs will contain: OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff And on the next boot, NAND core will rescan for bad blocks, then will see "0xff 0x19" pattern, and will mark all blocks as bad ones. To fix the issue we should implement our own bad block pattern: just one byte at OOB start. Though, this will work only for x8 chips. For x16 chips two bytes must be checked. Since ELBC driver does not support x16 NANDs (yet), we're safe for now. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: add NAND driver for S3C64XXGuennadi Liakhovetski2008-08-31-0/+320
| | | | | | Based on the original S3C64XX NAND driver by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-08-14-55/+55
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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