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* ppc4xx: Move ppc4xx headers to powerpc include directoryStefan Roese2010-09-23-1/+1
| | | | | | | | | This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
* nand/davinci: make sure ECC calculation has really startedWolfram Sang2010-09-13-1/+14
| | | | | | | | | | Due to a register glitch (result code <4 might show up right after the start-calculation-bit was set), make sure the ECC has really started. See 1c3275b656045aff9a75bb2c9f3251af1043ebb3 in the kernel. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Sandeep Paulraj <s-paulraj@ti.com>
* mtd: nand: supress 'unknown NAND' warning if no nand is foundSteve Sakoman2010-09-08-3/+6
| | | | | | | | | | | | | | | This printk was added recently and results in ugly output on systems with no NAND: NAND: nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x00, Chip ID: 0x00 0 MiB instead of: NAND: 0 MiB Signed-off-by: Steve Sakoman <steve@sakoman.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-11/+7
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2010-07-14-8/+8
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| * Blackfin: bfin_nand: convert to portmux frameworkMike Frysinger2010-07-13-8/+8
| | | | | | | | | | | | | | | | Rather than bang MMRs directly, use the new portmux framework to handle the details. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Acked-by: Scott Wood <scottwood@freescale.com>
* | mtd: nand_plat: add simple GPIO framework DEV_READY optionMike Frysinger2010-07-08-0/+11
| | | | | | | | | | | | | | | | Make it easy to use GPIOs for the DEV_READY pin by using the common GPIO framework. Also make the NAND_PLAT_INIT() define optional. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* | NAND: add Toshiba TC58NVG0 identifierFlorian Fainelli2010-07-08-0/+1
| | | | | | | | | | | | | | The Toshiba TC58NVG0* parts are 128Mbytes x 8 bits 3.3V parts with the 0xD1 identifier. Add these to the list of known devices IDs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* | NAND: show manufacturer and device ID for unknown chipsFlorian Fainelli2010-07-08-1/+5
|/ | | | | | | | When the NAND part is not supported, it is useful to show the manufacturer and device ID to help debugging and reporting. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Blackfin: nand: drain the write buffer before returningAndrew Caldwell2010-05-26-1/+6
| | | | | | | | | | | | | The current Blackfin nand write function fills up the write buffer but returns before it has had a chance to drain. On faster systems, this isn't a problem as the operation finishes before the ECC registers are read, but on slower systems the ECC may be incomplete when the core tries to read it. So wait for the buffer to drain once we're done writing to it. Signed-off-by: Andrew Caldwell <Andrew.Caldwell@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* at91: add hwecc method for nandNikolay Petukhov2010-03-23-0/+301
| | | | | | | This is a patch to use the hardware ECC controller of the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
* TI: Davinci: NAND Driver CleanupCyril Chemparathy2010-03-23-59/+69
| | | | | | | Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy <cyril@ti.com>
* mod change 755 => 644 for multiple filesThomas Weber2010-03-21-0/+0
| | | | | | | | I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' Signed-off-by: Thomas Weber <swirl@gmx.li> Add some more: neither Makefile nor config.mk need execute permissions. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-3/+1
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Nand mxc_nand add v1.1 controller supportJohn Rigby2010-01-27-71/+546
| | | | | | | | Add support for version 1.1 of the nfc nand flash controller which is on the i.mx25 soc. Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Scott Wood <scottwood@freescale.com>
* SPEAr : nand driver support for SPEAr SoCsVipin KUMAR2010-01-23-0/+125
| | | | | | | | SPEAr SoCs contain an FSMC controller which can be used to interface with a range of memories eg. NAND, SRAM, NOR. Currently, this driver supports interfacing FSMC with NAND memories Signed-off-by: Vipin <vipin.kumar@st.com>
* MXC: Add large page oob layout for i.MX31 NAND controller.Magnus Lilja2010-01-19-0/+12
| | | | | | | | | | | | | Import the large page oob layout from Linux mxc_nand.c driver. The CONFIG_SYS_NAND_LARGEPAGE option is used to activate the large page oob layout. Run time detection is not supported as this moment. This has been tested on the i.MX31 PDK board with a large page NAND device. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* mxc_nand: Update driver to work with i.MX31.Magnus Lilja2010-01-19-3/+31
| | | | | | Tested on i.MX31 Litekit. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+13
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| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-14/+11
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | Davinci: davinci_nand.c performance enhancmentsNick Thompson2010-01-06-54/+146
|/ | | | | | | | | | | Introduces various optimisations that approximately triple the read data rate from NAND when run on da830evm. Most of these optimisations depend on the endianess of the machine and most of them are very similar to optimisations already present in the Linux Kernel. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
* Merge branch 'next' of ../nextWolfgang Denk2009-12-15-61/+193
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| * common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-4/+0
| | | | | | | | | | | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
| * Merge branch 'master' into nextWolfgang Denk2009-12-07-1/+1
| |\ | | | | | | | | | | | | | | | | | | Conflicts: lib_generic/zlib.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Add a unified s3c24x0 header filekevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a unified s3c24x0 cpu header file that selects the header file for the specific s3c24x0 cpu from the SOC and CPU configs defined in board config file. This removes the current chain of s3c24-type #ifdef's from the s3c24x0 code. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s3c64xx: move s3c64xx header files to asm-arm/arch-s3c64xxMinkyu Kang2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | This patch moves the s3c64xx header files from include/ to include/asm-arm/arch-s3c64xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Move s3c24x0 header files to asm-arm/arch-s3c24x0/kevin.morfitt@fearnside-systems.co.uk2009-11-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves the s3c24x0 header files from include/ to include/asm-arm/arch-s3c24x0/. checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due to a non-UTF8 character in David M?ller's name: ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8 #489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3: + * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch As David's name correctly contains a non-UTF8 character I haven't fixed these errors. The 3 warnings were all because of the use of 'volatile' in s3c24x0.h: WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35: +typedef volatile u8 S3C24X0_REG8; +typedef volatile u16 S3C24X0_REG16; +typedef volatile u32 S3C24X0_REG32; I'll fix these errors in another patch. Tested by running MAKEALL for ARM8 targets and ensuring there were no new errors or warnings. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | NAND: Add Support for 4K page size in DaVinci NAND driverSandeep Paulraj2009-11-20-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NAND devices with a page size of 4K in the DaVinci NAND driver. The layout matches the layout that TI uses for 4K page size NAND devices in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | S3C2410 NAND Flash Add Missing FunctionHui.Tang2009-11-18-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | This patch add nand_read_buf() for S3C2410 NAND SPL. In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip, so nand->select_chip should also be initialized. Signed-off-by: Hui.Tang <zetalabs@gmail.com>
| * | NAND: Update read_read_subpage API checkSandeep Paulraj2009-11-18-1/+1
| | | | | | | | | | | | | | | | | | | | | This patch updates a check condition in the NAND driver. The check condition is similat to what is in linux/next. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | fsl_elbc_nand: remove the bbt descriptors relocation fixupMingkai Hu2009-11-13-4/+0
| | | | | | | | | | | | | | | | | | | | | The commit 66372fe2 manually relocated the bbt pattern pointer, which can be removed by using full relocation. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
| * | NAND: fix "raw" reads with ECC syndrome layoutsDavid Brownell2009-11-13-4/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The syndrome based page read/write routines store ECC, and possibly other "OOB" data, right after each chunk of ECC'd data. With ECC chunk size of 512 bytes and a large page (2KiB) NAND, the layout is: data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines use a traditional layout -- data OOB, disregarding the prepad and postpad values -- so when they're used with that type of ECC hardware, those calls mix up the data and OOB. Which means, in particular, that bad block tables won't be found on startup, with data corruption and related chaos ensuing. The current syndrome-based drivers in mainline all seem to use one chunk per page; presumably they haven't noticed such bugs. Fix this, by adding read/write page_raw_syndrome() routines as siblings of the existing non-raw routines; "raw" just means to bypass the ECC computations, not change data and OOB layout. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
| * | NAND: Don't walk past end of oobfree[]Sandeep Paulraj2009-11-13-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | When computing oobavail from the list of free areas in the OOB, don't assume there will always be an unused slot at the end. This syncs up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Update check condition for nand_read_page_hwecc APISandeep Paulraj2009-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch updates the check condition for determining whether the ECC corrections has failed. This makes it similar to what is in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Updating comments/explanations in the NAND driverSandeep Paulraj2009-11-13-4/+8
| | | | | | | | | | | | | | | | | | | | | Patch updates the comments and explanations for the arguments to various functions. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Subpage shift for ecc_steps equal to 16Sandeep Paulraj2009-11-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally part of Thomas Gleixner's patch for adding support for 4KiB pages. This is not part of the U-Boot NAND driver so updating the driver with this to sync up with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Remove commented out codeSandeep Paulraj2009-11-13-1/+0
| | | | | | | | | | | | | | | | | | Patch removes already commented out dead code Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Correct the "chip_shift" calculationSandeep Paulraj2009-11-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch updates the "chip_shift" calculation in the NAND driver. This is being done to sync up the NAND driver with the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * | NAND: Update to support 64 bit device sizeSandeep Paulraj2009-11-13-28/+39
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for NANDs greater than 2 GB. Patch is based on the MTD NAND driver in the kernel. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | nand: Fix access to last block in NAND devicesStefan Roese2009-12-11-2/+2
| |/ |/| | | | | | | | | | | | | | | Currently, the last block of NAND devices can't be accessed. This patch fixes this issue by correcting the boundary checking (off-by-one error). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
* | Fix computation in nand_util.c:get_len_incl_badDaniel Hobi2009-12-07-1/+1
|/ | | | | | | | | | | | | | | Depending on offset, flash size and the number of bad blocks, get_len_incl_bad may return a too small value which may lead to: 1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the bad block aware read/write code. This may hurt performance, but does not have any adverse effects. 2) If there are bad blocks, the nand_{read,write}_skip_bad may choose the bad block unaware read/write code (if len_incl_bad == *length) which leads to corrupted data. Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
* Clean-up of s3c24x0 nand driverkevin.morfitt@fearnside-systems.co.uk2009-10-13-37/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patches 1/4, 2/4 and 3/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Conditionally perform common relocation fixupsPeter Tyser2009-10-03-0/+2
| | | | | | | | | | | Add #ifdefs where necessary to not perform relocation fixups. This allows boards/architectures which support relocation to trim a decent chunk of code. Note that this patch doesn't add #ifdefs to architecture-specific code which does not support relocation. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* NAND: davinci: Fix warnings when 4-bit ECC not usedScott Wood2009-09-28-2/+1
| | | | | | | | | I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mpc512x. Micron nand flash needs a reset before a read command is issued.Paul Gibson2009-09-22-0/+1
| | | | | Micron nand flash needs a reset before a read command is issued. The current mpc5121_nfc driver ignores the reset command.
* ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-2/+2
| | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* mxc_nand: Remove Freescale's "All Rights Reserved."Scott Wood2009-09-04-1/+1
| | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-2/+282
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRSTSandeep Paulraj2009-08-26-0/+59
| | | | | | | | | | | | | | | | | This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
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