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* NAND: davinci: choose correct 1-bit h/w ECC regLaurence Withers2011-10-10-13/+13
| | | | | | | | | | | | | | | | | | | In nand_davinci_readecc(), select the correct NANDF<n>ECC register based on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. This allows 1-bit hardware ECC to work with chip select other than CS2. Note this now matches the usage in nand_davinci_enable_hwecc(), which already had the correct handling, and allows refactoring to a single function encapsulating the register read. Without this fix, writing NAND pages to a chip not wired to CS2 would result in in the ECC calculation always returning FFFFFF for each 512-byte segment, and reading back a correctly written page (one with ECC intact) would always fail. With this fix, the ECC is written and verified correctly. Signed-off-by: Laurence Withers <lwithers@guralp.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand, trivial : use symbolic ECC start commandBen Gardiner2010-10-17-1/+2
| | | | | | | | | | | The ECC calculations were started by writing 1 << 13 to the nand FCR register; that value is also defined as DAVINCI_NANDFCR_4BIT_CALC_START in emif_defs.h. This patch substitutes the macro DAVINCI_NANDFCR_4BIT_CALC_START for the magic number '1 << 13'. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* nand/davinci: make sure ECC calculation has really startedWolfram Sang2010-09-13-1/+14
| | | | | | | | | | Due to a register glitch (result code <4 might show up right after the start-calculation-bit was set), make sure the ECC has really started. See 1c3275b656045aff9a75bb2c9f3251af1043ebb3 in the kernel. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Cc: Sandeep Paulraj <s-paulraj@ti.com>
* TI: Davinci: NAND Driver CleanupCyril Chemparathy2010-03-23-59/+69
| | | | | | | Modified to use IO accessor routines consistently. Eliminated volatile usage to keep checkpatch.pl happy. Signed-off-by: Cyril Chemparathy <cyril@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-01-12-14/+13
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| * Davinci: NAND enable ECC even when not in NAND boot modeNick Thompson2010-01-04-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Davinci: NAND enable ECC even when not in NAND boot mode On Davinci platforms, the default NAND device is enabled (for ECC) in low level boot code when NAND boot mode is used. If booting in another mode, NAND ECC is not enabled. The driver should make sure ECC is enabled regardless of boot mode if NAND is configured in U-Boot. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
| * Davinci: Configurable NAND chip selectsNick Thompson2010-01-04-14/+11
| | | | | | | | | | | | | | | | | | | | Davinci: Configurable NAND chip selects Add a CONFIG_SYS_NAND_CS setting to all davinci configs and use it to setup the NAND controller in the davinci_nand mtd driver. Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
* | Davinci: davinci_nand.c performance enhancmentsNick Thompson2010-01-06-54/+146
|/ | | | | | | | | | | Introduces various optimisations that approximately triple the read data rate from NAND when run on da830evm. Most of these optimisations depend on the endianess of the machine and most of them are very similar to optimisations already present in the Linux Kernel. Signed-off-by: Nick Thompson <nick.thompson@ge.com>
* NAND: Add Support for 4K page size in DaVinci NAND driverSandeep Paulraj2009-11-20-7/+16
| | | | | | | | This patch adds support for NAND devices with a page size of 4K in the DaVinci NAND driver. The layout matches the layout that TI uses for 4K page size NAND devices in the kernel NAND driver. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* NAND: davinci: Fix warnings when 4-bit ECC not usedScott Wood2009-09-28-2/+1
| | | | | | | | | I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support" applied when I pushed the tree last merge window, and missed these fixes which were in v3 of that patch. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj2009-08-26-2/+282
| | | | | | | | This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Typo fix: use CONFIG_SOC_DM644X, not CONFIG_SOC_DM646.David Brownell2009-07-16-1/+1
| | | | | Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand chipselect/init cleanupDavid Brownell2009-07-07-20/+8
| | | | | | | | | | | | | | | | | Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC)David Brownell2009-07-07-205/+13
| | | | | | | | | | | | | | | | | | | | | | Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* davinci_nand: cleanup I (minor)David Brownell2009-07-07-33/+22
| | | | | | | | | | | | | | | | | | | | | | | | Minor cleanup for DaVinci NAND code: - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips). - Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them - Use the standard waitfunc; we don't need a custom version - Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ARM DaVinci: EMIF settingsThomas Lange2009-07-06-9/+3
| | | | | | | | | | | NAND module should not modify EMIF registers unrelated to CS2 that is used for NAND, i.e. do not modify EWAIT config register or registers for other Chip Selects. Without this patch, EMIF configurations made in board_init() will be invalidated. Signed-off-by: Thomas Lange <thomas@corelatus.se>
* davinci: move nand driver to drivers/mtd/nandJean-Christophe PLAGNIOL-VILLARD2009-03-30-0/+466
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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