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* | mmc-uclass: correct the device numberKever Yang2016-07-31-3/+3
| | | | | | | | | | | | | | | | | | Not like the mmc-legacy which the devnum starts from 1, it starts from 0 in mmc-uclass, so the device number should be (devnum + 1) in get_mmc_num(). Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: dw_mmc: reduce timeout detection cycleXu Ziyuan2016-07-27-1/+1
| | | | | | | | | | | | | | | | | | It's no need to speed 10 seconds to wait the mmc device out from busy status. 500 milliseconds enough. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* | dm: socfpga: mmc: Support CONFIG_BLKSimon Glass2016-07-27-1/+31
| | | | | | | | | | | | Update the driver to support using driver model for block devices. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: zynq: Convert zynq to use driver model for MMCSimon Glass2016-07-27-5/+34
| | | | | | | | | | | | | | Move zynq to the latest driver model support by enabling CONFIG_DM_MMC, CONFIG_DM_MMC_OPS and CONFIG_BLK. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: dwmmc: use the callback functions as staticJaehoon Chung2016-07-27-2/+2
| | | | | | | | | | | | | | | | | | There are no places to call these functions. It should be used the callback function. Then it can be used as static functions. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | mmc: rockchip: add SDHCI driver support for rockchip socKever Yang2016-07-25-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rockchip rk3399 using arasan sdhci-5.1 controller. This patch add the controller support to enable mmc device with full driver-model support, tested on rk3399 evb board. According to my test result, this driver should be OK, the command "part list mmc 0" can result in a right output, but all the mmc command failed like this: => mmc info No MMC device available Command failed, result=1 The result of get_mmc_num in cmd/mmc.c is always 0? Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-4/+3
| | | | | | | | | | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | mmc: sdhci: Disable internal clock enable bitSiva Durga Prasad Paladugu2016-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | Disable internal clock by clearing the internal clock enable bit. This bit needs to be cleared too when we stop the SDCLK for changing the frequency divisor. This bit should be set to zero when the device is not using the Host controller. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-16-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a number of typos, including: * "compatble" -> "compatible" * "eanbeld" -> "enabled" * "envrionment" -> "environment" * "FTD" -> "FDT" (for "flattened device tree") * "ommitted" -> "omitted" * "overriden" -> "overridden" * "partiton" -> "partition" * "propogate" -> "propagate" * "resourse" -> "resource" * "rest in piece" -> "rest in peace" * "suport" -> "support" * "varible" -> "variable" Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-07-15-22/+5
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| * | sunxi: Use BROM stored boot_media value to determine our boot-sourceHans de Goede2016-07-15-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we know that the BROM stores a value indicating the boot-source at the beginning of SRAM, use that instead of trying to recreate the BROM's boot probing. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi: mmc: increase status register polling rate for data transfersTobias Doerffel2016-07-15-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With a recent bunch of SD3.0 cards in our A20-based board we experienced data transfer rates of about 250 KiB/s instead of 10 MiB/s with previous cards from the same vendor (both 4 GB/class 10). By increasing status register polling rate from 1 kHz to 1 MHz we were able to reach the original transfer rates again. With the old cards we now even reach about 16 MiB/s. Signed-off-by: Tobias Doerffel <tobias.doerffel@ed-chemnitz.de> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2016-07-15-63/+85
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| * | | mmc: exynos_dw_mmc: support the Driver mode for ExynosJaehoon Chung2016-07-12-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch support the driver mode for exynos dwmmc controller. To support the legacy model, maintained the existing code. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: use the 4bit bus-width by defaultJaehoon Chung2016-07-12-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is not "samsung,bus-width" property, use the 4bit buswidth by default. Almost all Exnyos SoCs support at least 4bit buswidth. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: clean the unused and unnecessary codesJaehoon Chung2016-07-12-22/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean the unused and unnecessary codse. This patch is one of them for preparing to use DM. Because it's easy to maintain and combine DM after cleaning codes. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: add the error control for checking indexJaehoon Chung2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PERIPH_ID_SDMMC4(131) is not continous value with PERIPH_ID_SDMMC0(75). If there is no 'index' property in fdt, then dev_index should be assigned to dev_id(Peripheral ID). At this time, dev_index should be "56". It means Exynos SoC has "56" numbers of DWMMC IP. To prevent this behavior, it needs to check the maximum device index. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: remove #ifdef for OF_CONTROLJaehoon Chung2016-07-12-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removed #ifdef for OF_CONTROL. It might use 'OF_CONTROL' by default. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | | mmc: exynos_dw_mmc: remove the unused functionJaehoon Chung2016-07-12-36/+0
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | This function have maintained for supporting Non-FDT. Now, Almost all SoC are changed to fdt style. So there are no that this function is called anywhere. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | rockchip: mmc: Update the driver to support of-platdataSimon Glass2016-07-14-3/+26
| | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288. This requires decoding the of-platdata struct and setting up the device from that. Also the driver needs to be renamed to match the string that of-platdata will search for. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | rockchip: mmc: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-15/+17
| |/ |/| | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: msmsdhic: Drop old MMC codeSimon Glass2016-07-11-16/+1
| | | | | | | | | | | | Now that we have fully moved to driver model, drop the old code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: msm_sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPSSimon Glass2016-07-11-2/+44
| | | | | | | | | | | | | | Add support for using driver model for block devices and MMC operations in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: sdhci: Support CONFIG_BLK and CONFIG_DM_MMC_OPSSimon Glass2016-07-11-1/+39
| | | | | | | | | | | | | | Add support for using driver model for block devices and MMC operations in this driver. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: sdhci: Refactor configuration setup to support DMSimon Glass2016-07-11-48/+59
| | | | | | | | | | | | | | Move the configuration setting into a separate function which can be used by the driver-model code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: sandbox: Convert to use CONFIG_CMD_MMC_OPSSimon Glass2016-07-11-11/+6
| | | | | | | | | | | | Update the sandbox MMC emulation to use driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: rockchip: Enable CONFIG_DM_MMC_OPS for all boardsSimon Glass2016-07-11-1/+2
| | | | | | | | | | | | | | Enable this option to move rockchip over to use driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: dwmmc: Support CONFIG_DM_MMC_OPSSimon Glass2016-07-11-0/+33
| | | | | | | | | | | | Add support to dwmmc for using driver model for MMC operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: Add a way to use driver model for MMC operationsSimon Glass2016-07-11-3/+93
| | | | | | | | | | | | | | | | | | | | | | | | The driver model conversion for MMC has moved in small steps. The first step was to have an MMC device (CONFIG_DM_MMC). The second was to use a child block device (CONFIG_BLK). The final one is to use driver model for MMC operations (CONFIG_DM_MMC_OP). Add support for this. The immediate priority is to make all boards that use DM_MMC also use those other two options. This will allow them to be removed. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: Move tracing code into separate functionsSimon Glass2016-07-11-15/+45
| | | | | | | | | | | | | | Move this code into separate functions so that it can be used from the uclass also. Add static inline versions for when the option is disabled. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: rockchip: Support only CONFIG_BLKSimon Glass2016-07-11-11/+0
| | | | | | | | | | | | Since all Rockchip boards use CONFIG_BLK, we can remove this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: Move MMC boot code into its own fileSimon Glass2016-07-11-125/+146
| | | | | | | | | | | | | | Rather than having an #ifdef in the main mmc.c file, control this feature from the Makefile by moving the code into its own file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: Move non-CONFIG_BLK code into mmc_legacy.cSimon Glass2016-07-11-95/+91
| | | | | | | | | | | | Rather than having #ifdef in mmc.c, move this code into the legacy file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: mmc: Move CONFIG_BLK code into the mmc uclassSimon Glass2016-07-11-82/+83
| | | | | | | | | | | | Rather than having #ifdef in mmc.c, move this code into the uclass file. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: Add function declarations for mmc_bread() and mmc_switch_part()Simon Glass2016-07-11-5/+21
|/ | | | | | | These private functions are used both in the driver-model implementation and in the legacy code. Add them to the header. Signed-off-by: Simon Glass <sjg@chromium.org>
* mmc: msm_sdhci: Set mmc->dev pointer in msm_sdc_probe()Mateusz Kulikowski2016-07-08-1/+6
| | | | | | | | | | | MMC core expects (now) valid mmc->dev pointer. During conversion in commit cffe5d86 not every driver was updated. This patch fixes crash while accessing MMC on boards using Qualcomm SDHCI controller. Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* mmc: increase MMC SDHCI read status timeoutSteve Rae2016-07-01-2/+3
| | | | | | | | | | | | | | | | | | | | | | Otherwise, ocassionally see errors like this: Flashing sparse image at offset 2078720 Flashing Sparse Image sdhci_send_command: Timeout for status update! mmc fail to send stop cmd write_sparse_image: Write failed, block #2181088 [0] This does not affect the actual writing speed, which is controlled by the default value: CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT It only increases the retries when reading: SDHCI_INT_STATUS to avoid the timeout error. Signed-off-by: Steve Rae <steve.rae@raedomain.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-28-14/+54
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| * mmc: fsl: introduce wp_enablePeng Fan2016-06-28-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introudce wp_enable. To check WPSPL, wp_enable needs to be set to 1 in board code. Take i.MX6UL for example, for some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller. If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl_esdhc: Update clock enable bits for USDHCYe Li2016-06-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USDHC moves the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it. So in this patch, we change to use the vendorspec registers for these bits operation. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * mmc: fsl: reset to normal boot mode when eMMC fast bootPeng Fan2016-06-28-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors. This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode. Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: York Sun <york.sun@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mmc: dw_mmc: fix the wrong AND operationJaehoon Chung2016-06-27-2/+2
|/ | | | | | | | | | These condition checking are wrong. Original Author's intention might be "&" instead of "&&". It can know whether receive or transmit data request with BIT[4]/BIT[5] of RINTSTS register. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* mmc: add MMC_VERSION_5_1Stefan Wahren2016-06-20-0/+3
| | | | Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
* clk: convert API to match reset/mailbox styleStephen Warren2016-06-19-14/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-13-4/+4
| | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xxHeiko Schocher2016-06-09-0/+1
| | | | | | | Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: revert mmc: Handle switch error status bit in MMC card statusHeiko Schocher2016-06-09-3/+1
| | | | | | | | | revert patch: commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status to get eMMC working on shc board Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-06-04-5/+4
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| * mmc: fsl_esdhc: fix check_and_invalidate_dcache_range functionYangbo Lu2016-06-03-5/+4
| | | | | | | | | | | | | | | | | | In function check_and_invalidate_dcache_range(), there are incorrect start address and end address of the dcache range calculated for Layerscape platforms. This patch is to fix this issue. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mmc: tegra: add basic Tegra186 supportStephen Warren2016-05-31-1/+31
|/ | | | | | | | | | | | | | | | | | | | | | Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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