summaryrefslogtreecommitdiff
path: root/drivers/mmc
Commit message (Collapse)AuthorAgeLines
* arm: socfpga: Nuke useless includeMarek Vasut2016-04-10-1/+0
| | | | | | | | | | The dwmmc.h include was forgotten during the migration of dwmmc probing to DM. Since the shiny DM is in place now, remove this relic of the past. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
* fsl: esdhc: support driver modelPeng Fan2016-04-06-40/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support Driver Model for fsl esdhc driver. 1. Introduce a new structure struct fsl_esdhc_priv 2. Refactor fsl_esdhc_initialize which is originally used by board code. - Introduce fsl_esdhc_init to be common usage for DM and non-DM - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part. - The original API for board code is still there, but we use 'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it. 3. All the functions are changed to use 'struct fsl_esdhc_priv', except fsl_esdhc_initialize. 4. Since clk driver is not implemented, use mxc_get_clock to geth the clk and fill 'priv->sdhc_clk'. Has been tested on i.MX6UL 14X14 EVK board: " =>dm tree .... simple_bus [ + ] | `-- aips-bus@02100000 mmc [ + ] | |-- usdhc@02190000 mmc [ + ] | |-- usdhc@02194000 .... => mmc list FSL_SDHC: 0 (SD) FSL_SDHC: 1 (SD) " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Yangbo Lu <yangbo.lu@nxp.com> Cc: Hector Palacios <hector.palacios@digi.com> Cc: Eric Nelson <eric@nelint.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Tested-By: Eric Nelson <eric@nelint.com> Reviewed-by: York Sun <york.sun@nxp.com>
* mmc: Add support for Qualcomm SDHCI controllerMateusz Kulikowski2016-04-01-0/+190
| | | | | | | | | | | Add support for SD/eMMC controller present on some Qualcomm Snapdragon devices. This controller implements SDHCI 2.0 interface but requires vendor-specific initialization. Driver works in PIO mode as ADMA is not supported by U-Boot (yet). Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-04-01-1/+5
|\
| * sunxi: Add support for Allwinner A64 SoCsSiarhei Siamashka2016-04-01-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: Explicitly cast u32 pointer conversionsAlexander Graf2016-04-01-1/+1
| | | | | | | | | | | | | | | | | | | | | | Some parts of the sunxi code cast explicitly between u32 values and pointers. This is not a problem in practice, because all 64bit SoCs today only use the lower 32 bits for their phyical address space. But we need to make sure that the compiler is sure this is not an accident as well. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | mmc: uniphier: use devm_get_addr() to get base addressMasahiro Yamada2016-04-01-3/+6
|/ | | | | | | | | Currently, fdtdec_get_addr_size() does not support the address translation, so it cannot handle device trees with non-straight "ranges" properties. (This would be a problem with DTS for UniPhier ARMv8 SoCs.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: Print send_cmd response only when return value is zeroBin Meng2016-03-27-38/+42
| | | | | | | | send_cmd response is valid only when no error happened. If an error occured, let mmc_send_cmd() print the return value to aid debugging. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: Fix switch..case indentionBin Meng2016-03-27-70/+70
| | | | | | | Correct the indention level of switch..case statements. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: bcm2835: fix 64-bit build warningStephen Warren2016-03-27-1/+1
| | | | | | | | Fixes: drivers/mmc/bcm2835_sdhci.c: In function ‘bcm2835_sdhci_init’: drivers/mmc/bcm2835_sdhci.c:181:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* dwmmc: Increase retry timeoutAlexander Graf2016-03-15-1/+1
| | | | | | | | | | | | | | When enable dcache on HiKey, we're running into MMC command timeouts because our retry loop is now faster than the eMMC (or an external SD card) can answer. Increase the retry count to the same as the timeout value for status reports. The real fix is obviously to not base this whole thing on a cycle counter but on real wall time, but that would be slightly more intrusive. Signed-off-by: Alexander Graf <agraf@suse.de>
* omap_hsmmc: Board-specific TWL6030 MMC power initializationPaul Kocialkowski2016-03-15-4/+2
| | | | | | | | | | Boards using the TWL6030 regulator may not all use the LDOs the same way. Some might also not use MMC1 at all, so VMMC would't have to be enabled. This delegates TWL6030 MMC power initializations to board-specific functions, that may still call twl6030_power_mmc_init for the default behavior. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* power: twl6030: Device-index-specific MMC power initializationPaul Kocialkowski2016-03-15-2/+2
| | | | | | | | Not every device has multiple MMC slots available, so it makes sense to enable only the required LDOs for the available slots. Generic code in omap_hsmmc will enable both VMMC and VAUX1, in doubt. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-03-14-31/+31
|\
| * dm: block: Rename device number member dev to devnumSimon Glass2016-03-14-22/+22
| | | | | | | | | | | | | | | | | | This is a device number, and we want to use 'dev' to mean a driver model device. Rename the member. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
| * dm: part: Rename some partition functionsSimon Glass2016-03-14-1/+1
| | | | | | | | | | | | | | | | Rename three partition functions so that they start with part_. This makes it clear what they relate to. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Stephen Warren <swarren@nvidia.com>
| * dm: Drop the block_dev_desc_t typedefSimon Glass2016-03-14-8/+8
| | | | | | | | | | | | | | | | | | Use 'struct' instead of a typdef. Also since 'struct block_dev_desc' is long and causes 80-column violations, rename it to struct blk_desc. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | lib/crc16.c: Rename cyg_crc16() to crc16_ccitt() and add crc start valueStefan Roese2016-03-14-2/+2
|/ | | | | | | | | | | | | The original name of this function is unclear. This patch renames this CRC16 function to crc16_ccitt() matching its name with its implementation. To make the usage of this function more flexible, lets add the CRC start value as parameter to this function. This way it can be used by other functions requiring different start values than 0 as well. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* mmc: uniphier: add driver for UniPhier SD/MMC host controllerMasahiro Yamada2016-02-29-0/+758
| | | | | | | Add a driver for the on-chip SD/eMMC host controller used by UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* mmc: Kconfig: Add Arasan SDHCI entryMichal Simek2016-02-22-0/+6
| | | | | | Add Arasan SDHCI entry to Kconfig and fix all references. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* tegra: mmc: Fix comments in the MMC driver initSimon Glass2016-02-16-2/+2
| | | | | | | Fix the SoC names in two comments. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* Use correct spelling of "U-Boot"Bin Meng2016-02-06-1/+1
| | | | | | | | | | Correct spelling of "U-Boot" shall be used in all written text (documentation, comments in source files etc.). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-3/+12
|\
| * mmc: atmel: Properly fix clock configurationGregory CLEMENT2016-01-27-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timing issue occurs on eMMC not only when modifying the frequency but also for all the switch command(CMD6). According to the MMC spec waiting 8 clocks after a switch command would be the thing to do. This patch allows fixing CPU hang observed when trying to changing the bus width on a eMMC on SAMA5D4. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Marek Vasut <marex@denx.de> # on DENX MA5D4EV Acked-by: Marek Vasut <marex@denx.de> Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> # on atngw100 Acked-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixed minor checkpatch warning] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | drivers: mmc: add driver for Microchip PIC32 SDHCI controller.Andrei Pistirica2016-02-01-1/+72
| | | | | | | | | | | | | | | | | | | | | | This driver implements platform specific glue and fixups for PIC32 internal SDHCI controller. Signed-off-by: Andrei Pistirica <andrei.pistirica@microchip.com> Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-27-5/+9
|\ \
| * | mmc: fsl_esdhc: set Abort command type for CMD12Yangbo Lu2016-01-27-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need to be set an Abort command type when they are sent. So, we remove all chip-specific #ifdefs and make it available for all platforms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | mmc: fsl_esdhc: increase data transaction timeout to 500msYangbo Lu2016-01-27-1/+8
| |/ | | | | | | | | | | | | | | | | | | The MMC spec says "It is strongly recommended for hosts to implement more than 500ms timeout value even if the card indicates the 250ms maximum busy length." Even the previous value of 300ms is known to be insufficient for some cards. So, increase the timeout to 500ms. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | mmc: zynq_sdhci: Added qurik to disable high speedSiva Durga Prasad Paladugu2016-01-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add quirk to disable high speed incase the high speed was broken.This solves the issue where the the controller is used in High Speed Mode and the the hold time requirement for the JEDEC/MMC 4.41 specification is NOT met. This timing issue is not on all boards and hence provided config option to enable it when required. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Emil Lenchak <emill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | mmc: sdhci: Clear high speed if not supportedSiva Durga Prasad Paladugu2016-01-27-0/+4
| | | | | | | | | | | | | | | | | | Clear high speed bit if it was not supported by the driver. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Emil Lenchak <emill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | sdhci: zynq: Remove hardcoded value zero as min frequencySiva Durga Prasad Paladugu2016-01-27-1/+6
|/ | | | | | | | | Remove hardcoded value zero as min frequency and use config option CONFIG_ZYNQ_SDHCI_MIN_FREQ defined in board config Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* rockchip: Use a separate clock ID for clocksSimon Glass2016-01-21-8/+5
| | | | | | | | | | At present we use the same peripheral ID for clocks and pinctrl. While this works it is probably better to use the device tree clock binding ID for clocks. We can use the clk_get_by_index() function to find this. Update the clock drivers and the code that uses them. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: mmc: Use a pwrseq device if availableSimon Glass2016-01-21-0/+47
| | | | | | | Use the pwrseq uclass to find a suitable power sequence for the MMC device. If this is enabled in the device tree, we will pick it up automatically. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: mmc: Try to honour the sequence orderSimon Glass2016-01-20-5/+15
| | | | | | | | | | | | At present we add driver-model MMC devices in the order we find them. The 'alias' order is not honoured. It is difficult to fix this for the case where we have holes in the sequence. But for the common case where the devices are numbered from 0 without any gaps, we can add the devices to the internal data structures in this order. Signed-off-by: Simon Glass <sjg@chromium.org>
* Add more SPDX-License-Identifier tagsTom Rini2016-01-19-7/+2
| | | | | | | | | In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>
* mmc: rockchip: the non-removable property must point to emmchuang lin2016-01-15-0/+2
| | | | | | | | | the non-removable property point to sdcard before, it is wrong, it must point to emmc, correct it. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: store hwpart in the block deviceStephen Warren2016-01-13-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will allow us to have multiple block device structs each referring to the same eMMC device, yet different HW partitions. For now, there is still a single block device per eMMC device. As before, this block device always accesses whichever HW partition was most recently selected. Clients wishing to make use of multiple block devices referring to different HW partitions can simply take a copy of this block device once it points at the correct HW partition, and use each one as they wish. This feature will be used by the next patch. In the future, perhaps get_device() could be enhanced to return a dynamically allocated block device struct, to avoid the client needing to copy it in order to maintain multiple block devices. However, this would require all users to be updated to free those block device structs at some point, which is rather a large change. Most callers of mmc_switch_part() wish to permanently switch the default MMC block device's HW partition. Enhance mmc_switch_part() so that it does this. This removes the need for callers to do this. However, common/env_mmc.c needs to save and restore the current HW partition. Make it do this more explicitly. Replace use of mmc_switch_part() with mmc_select_hwpart() in order to remove duplicate code that skips the call if that HW partition is already selected. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* block: pass block dev not num to read/write/erase()Stephen Warren2016-01-13-14/+23
| | | | | | | | | | | This will allow the implementation to make use of data in the block_dev structure beyond the base device number. This will be useful so that eMMC block devices can encompass the HW partition ID rather than treating this out-of-band. Equally, the existence of the priv field is crying out for this patch to exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* dm: Convert PCI MMC over to use DM PCI APISimon Glass2016-01-12-8/+7
| | | | | | | | | | | | | | At present pci_mmc_init() does not correctly use the PCI function since the list it passes is not terminated. The array size passed to pci_mmc_init() is actually not used correctly. Fix this and adjust the pci_mmc_init() to scan all available MMC devices. Adjust this code to use the new driver model PCI API. This should move over to the new MMC uclass at some point. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* mmc: update MMC_ERASE argument to match Linux kernel.Eric Nelson2016-01-04-1/+1
| | | | | | | | | | | | | | | | | | | Table 41 of the JEDEC standard for eMMC says that bit 31 of the command argument is obsolete when issuing the ERASE command (CMD38) on page 115 of this document: http://www.jedec.org/sites/default/files/docs/jesd84-B45.pdf The SD Card Association Physical Layer Simplified Specification also makes no mention of the use of bit 31. https://www.sdcard.org/downloads/pls/part1_410.pdf The Linux kernel distinguishes between secure (bit 31 set) and non-secure erase, and this patch copies the macro names from include/linux/mmc/core.h. Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Eric Nelson <eric@nelint.com> Tested-by: Hector Palacios <hector.palacios@digi.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-01-03-2/+13
|\
| * ARM: imx: fsl_esdhc: fix usage of low 4 bits of sysctl registerEric Nelson2016-01-03-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Hector Palacios <hector.palacios@digi.com>
* | arm: socfpga: fix up a questionable macro for SDMMCDinh Nguyen2015-12-20-2/+3
| | | | | | | | | | | | | | | | Move the macro into the socfpga_dwmci_clksel(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Marek Vasut <marex@denx.de> [fix parenthesis in the sdmmc_mask]
* | mmc: mmc: Don't use sprintf when using tiny-printfSjoerd Simons2015-12-13-1/+3
| | | | | | | | | | | | | | There is no sprintf implementation in tiny-printf, so don't try to use it when tiny-printf if used. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-12-07-37/+30
|\ \
| * | zynq: sdhci: Move driver to DMMichal Simek2015-12-07-12/+32
| | | | | | | | | | | | | | | | | | | | | Move driver to DM Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | zynq: sdhci: Remove zynq_sdhci_of_init()Michal Simek2015-12-07-27/+0
| | | | | | | | | | | | | | | | | | Prepare for using DM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | zynq: sdhci: Calculate minimum frequency based on max frequencySiva Durga Prasad Paladugu2015-12-07-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Calculate the minimum sd clock based on max clock. This will be done by add_sdhci() if we pass minimum clock as zero. It also does based on SD host contoller version. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | mmc: dwmmc: socfpga: Convert to DMMarek Vasut2015-12-07-76/+60
|/ / | | | | | | | | | | | | | | | | | | | | Convert the SoCFPGA shim for registering the DWMMC driver to DM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
* | rockchip: mmc: get the fifo mode and fifo depth property from dtshuang lin2015-12-01-4/+17
| | | | | | | | | | | | | | | | rk3036 mmc do not have internal dma, so we use fifo mode when read and write data, we get the fifo mode and fifo depth property from dts, pass to dw_mmc driver. Signed-off-by: Lin Huang <hl@rock-chips.com>
generated by cgit v1.1 at 2024-11-12 21:14:04 +0000