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* tegra2: Modify MMC driver to handle power and cd GPIOsStephen Warren2011-12-09-7/+39
| | | | | | | | | | | | | | | | | | | | | | | Pass the GPIO numbers for power and card detect to tegra2_mmc_init(), and modify that function to perform all required GPIO initialization. This removes the need for board files to perform these operations. Move board_mmc_getcd() into tegra2_mmc.c now that the driver knows which GPIOs to use. Update affected call-sites in seaboard.c and harmony.c. Note that this change should make all SD ports work on Harmony, since the required GPIO setup is now being performed. v4: Fix prototype of tegra2_mmc_init() in board.h to match driver change. Remove prototype of gpio_config_mmc() from board.h Signed-off-by: Stephen Warren <swarren@nvidia.com> Cc: Andy Fleming <afleming@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]XMarek Vasut2011-12-06-5/+6
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* Revert "mmc: retry the cmd8 to meet 74 clocks requirement in the spec"Macpaul Lin2011-11-25-14/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit 02f3029f1810b99869254d0cf0a71946a008a728. This patch add 3 times retry to CMD8 because the Marvell mmc controller doesn't obey the power ramp up process in the SD specification 6.4.1. (Please refer to figure 6.1 and 6.2 in the specification.) The CMD0 should be send after power ramp up has been finished. However, the Marvell mmc contorller must do power ramp up after the first CMD0 command has been send. This patch also affect existing platforms like Nokia N900 and other platforms. Signed-off-by: Macpaul Lin <macpaul@andestech.com> Acked-by: Lei Wen <leiwen@marvell.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* mmc: mv_sdhci: Fix host version read for Armada100Ajay Bhargav2011-11-25-1/+4
| | | | | | | | sdhci_readw does not work for host version read in Armada100 series SoCs. This patch fix this issue by making a sdhci_readl call to get host version. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* davinci, mmc: fix gcc 4.6 build warningsHeiko Schocher2011-11-16-4/+3
| | | | | | | | | | | | | | Fix: davinci_mmc.c: In function 'dmmc_wait_fifo_status': davinci_mmc.c:72:7: warning: variable 'mmcstatus1' set but not used [-Wunused-but-set-variable] davinci_mmc.c: In function 'dmmc_busy_wait': davinci_mmc.c:89:7: warning: variable 'mmcstatus1' set but not used [-Wunused-but-set-variable] Delete the unused variable. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-11-16-12/+366
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: arm, davinci: add DAVINCI_MMC_CLKID arm, davinci_emac: fix driver bug if more then 3 PHYs are detected arm, davinci: da850/dm365 lowlevel cleanup omap5: Add omap5_evm board build support. omap4/5: Add support for booting with CH. omap5: emif: Add emif/ddr configurations required for omap5 evm omap5: clocks: Add clocks support for omap5 platform. omap5: Add minimal support for omap5430. omap: Checkpatch fixes omap4: make omap4 code common for future reuse GCC4.6: Squash warnings in onenand_base.c GCC4.6: Fix common/usb.c on xscale OneNAND: Add simple OneNAND SPL PXA: vpac270: Enable the new generic MMC driver PXA: Cleanup serial_pxa PXA: Drop csb226 and innokom boards (unmaintained) m28evk: Fix comment about the number of RAM banks mx31: Fix checkpatch warnings in generic.c mx31: Use proper IO accessor for GPR register mx31: Remove duplicate definition for GPR register qong: Use generic function for configuring GPR register M28EVK: Enable USB HOST support iMX28: Add USB HOST driver iMX28: Add USB and USB PHY register definitions M28: Add memory detection into SPL iMX28: Fix ARM vector handling M28: Add doc/README.m28 documentation M28: Add MMC SPL iMX28: Add support for DENX M28EVK board iMX28: Add u-boot.sb target to Makefile iMX28: Add image header generator tool iMX28: Add driver for internal RTC iMX28: Add GPMI NAND driver iMX28: Add APBH DMA driver iMX28: Add SPI driver iMX28: Add GPIO control iMX28: Add I2C bus driver iMX28: Add PINMUX control FEC: Add support for iMX28 quirks iMX28: Add SSP MMC driver iMX28: Initial support for iMX28 CPU MX25: zmx25: GCC4.6 fix build warnings da850: add new config file for AM18xx BeagleBoard: config: Switch to ttyO2 OMAP3: Change omap3_evm maintainer devkit8000: Fix NAND SPL on boards with 256MB NAND integrator: enable Vpp and disable flash protection integrator: add system controller header integrator: make flash writeable on boot integrator: use io-accessors for board init integrator: move text offset to config integrator: pass configs for core modules ARM: remove superfluous setting of arch_number in board specific code. SPL: Allow ARM926EJS to avoid compiling in the CPU support code integrator: do not test first part of the memory arm: a320: fix broken timer ARM: define CONFIG_MACH_TYPE for all ronetix boards dm646x: pass board revision info to kernel dm646x: add new configuration for dm6467T arm, davinci: Fix setting of the SDRAM configuration register arm, davinci: Remove the duplication of LPSC functions arm, davinci: Rename AM1808 lowlevel functions to DA850 da8xxevm: fix build error ARM: re-add MACH_TYPE_XXXXXX for VCMA9 board and add CONFIG_MACH_TYPE
| * omap: Checkpatch fixesSricharan2011-11-15-12/+14
| | | | | | | | | | | | | | | | | | Fixing them here so that when the files are reused in subsequent patches for omap5, avoids new checkpatch warnings. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * iMX28: Add SSP MMC driverMarek Vasut2011-11-11-0/+352
| | | | | | | | | | | | | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Acked-by: Andy Fleming <afleming@gmail.com>
* | Tegra2: mmc: Factor out mmc_wait_inhibit functionalityAnton staaf2011-11-12-19/+27
| | | | | | | | | | | | | | | | | | | | | | This is a well encapsulated section of mmc_send_cmd, by moving it to it's own function it increases the readability of mmc_send_cmd. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | Tegra2: mmc: Add data transfer completion timeoutAnton staaf2011-11-12-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when no expected completion condition occures in the mmc_send_cmd while loop that is waiting for a data transfer to complete the MMC driver just hangs. This patch adds an arbitrary 2 second timeout. If nothing we recognize occures within 2 seconds some diagnostic information is printed and we fail out. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | Tegra2: mmc: Support DMA restarts at buffer boundariesAnton staaf2011-11-12-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently if a DMA buffer straddles a buffer alignment boundary (512KiB) then the DMA engine will pause and generate a DMA interrupt. Since the DMA interrupt is not enabled it will hang the MMC driver. This patch adds support for restarting the DMA transfer. The SYSTEM_ADDRESS register contains the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | Tegra2: mmc: define register field values in tegra2_mmc.hAnton staaf2011-11-12-27/+85
| | | | | | | | | | | | | | | | | | | | | | | | This moves the magic numbers sprinkled about the MMC driver to a single location in the header file and gives them meaningful names. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Andy Fleming <afleming@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | MMC: PL180: Fix infinite loop with VExpress extended fifo implementationJon Medhurst (Tixy)2011-11-08-26/+0
|/ | | | | | | | | | | | | | | | | | | The new IO FPGA implementation for Versatile Express contains an MMCI (PL180) cell with the FIFO extended to 128 words. This causes the read_bytes() function to go into an infinite loop; as it will wait for for the half-full signal (SDI_STA_RXFIFOBR) if there are more than 8 words remaining (SDI_FIFO_BURST_SIZE), but it won't receive this signal once there are fewer than 64 words left to transfer. One possible fix is to add some build time configuration to change SDI_FIFO_BURST_SIZE for the new implementation. However, the problematic code only seems to exist as a small performance optimisation, so the solution implemented by this patch is to simply remove it. The error checking following the loop is also removed as this will be handled by code further down the function. Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Jon Medhurst <jon.medhurst@linaro.org>
* tegra2: Move MMC clock initialization into MMC driverStephen Warren2011-11-03-3/+9
| | | | | | | | | | | This centralizes knowledge of MMC clocking into the MMC driver. This also removes clock setup from the board files, which will simplify later changes that modify the Harmony board to support the correct set of MMC controllers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Cc: Andy Fleming <afleming@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* mmc: sdhci: fix sdma bug for large file transferLei Wen2011-11-03-1/+1
| | | | | | | | | SDHCI spec need to reset the sdma base address while the software try to accorss the 512k bytes address boundary. When meet such accross behavior, sdhci controller would generate a interrupt automatically, and software need handle this. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: add timeout for data transferLei Wen2011-11-03-1/+8
| | | | Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: add mmc structure for hostLei Wen2011-11-03-0/+1
| | | | | | | So that sdhci host would tell in the driver that the mmc current attributes. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: sdhci: fix cache flushLei Wen2011-11-03-1/+1
| | | | | | Only flush the memory range needed. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: CMD7:MMC_CMD_SELECT_CARD response fixAjay Bhargav2011-11-03-1/+1
| | | | | | | | | | | | | As per JEDEC document JESD84-A441 (page 105) response for CMD7 (MMC_CMD_SELECT_CARD) response should be R1 instead of R1b. In uboot we never take MMC to disconnected state and on powerup its always ideal state which later goes to stand-by state. from document footnote: R1 while selecting from Stand-By State to Transfer State; R1b while selecting from Disconnected State to Programming State. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
* mmc: test mmc bus width on startupLei Wen2011-11-03-18/+26
| | | | | | | | | | | | | | For we don't know mmc bus width from reading registers, the only way to check is to test. Current compare offset is: EXT_CSD_PARTITIONING_SUPPORT EXT_CSD_ERASE_GROUP_DEF EXT_CSD_REV EXT_CSD_HC_ERASE_GRP_SIZE EXT_CSD_SEC_CNT Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: change magic number to macro defineLei Wen2011-11-03-9/+12
| | | | | | | | Previous magic number is hard to parse its meaning, change it to respective macro definition Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: WOlfgang Denk <wd@denx.de>
* mmc: mv_sdhci: fix 8bus width access for 88SV331xV5Lei Wen2011-11-03-0/+33
| | | | | | | | | | | | Marvell 88SV331xV5 platform's sdhci host control is not very standard with the spec in the 8bit handling. It need to set its private register to switch to the 8bit mode which is not included in the standard sdhci registers. This patch mainly hacks the writeb method, and set its private register if it find the driver is going to switch to the 8bit mode. Signed-off-by: Lei Wen <leiwen@marvell.com>
* mmc: retry the cmd8 to meet 74 clocks requirement in the specLei Wen2011-11-03-2/+14
| | | | | | | | | | For some controller it has dynamic clock gating, and only toggle out clk when the first cmd0 send out, while some card strictly obey the 74 clocks rule, the interval may not be sufficient between the cmd0 and this cmd8, retry to fulfil the clock requirement. Signed-off-by: Lei Wen <leiwen@marvell.com> Tested-by: Marek Vasut <marek.vasut@gmail.com>
* PXA: Add MMC driver using the generic MMC frameworkMarek Vasut2011-11-03-0/+443
| | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2011-10-28-62/+37
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: ARM: Add Calxeda Highbank platform dkb: make mmc command as default enabled Marvell: dkb: add mmc support ARM: pantheon: add mmc definition davinci: remove config.mk file from the sources ARM:AM33XX: Add support for TI AM335X EVM ARM:AM33XX: Added timer support ARM:AM33XX: Add emif/ddr support ARM:AM33XX: Add clock definitions ARM:AM33XX: Added support for AM33xx omap3/emif4: fix registers definition davinci: remove obsolete macro CONFIG_EMAC_MDIO_PHY_NUM davinci: emac: add support for more than 1 PHYs davinci: emac: add new features to autonegotiate for EMAC da850evm: Move LPSC configuration to board_early_init_f() omap4_panda: Build in cmd_gpio support on panda omap: Don't use gpio_free to change direction to input mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unset OMAP3: overo : Add environment variable optargs to bootargs OMAP3: overo: Move ethernet CS4 configuration to execute based on board id OMAP3: overo : Use ttyO2 instead of ttyS2. da830: add support for NAND boot mode dm36x: revert cache disable patch dm644X: revert cache disable patch devkit8000: Add malloc space omap: spl: fix build break due to changes in FAT OMAP3 SPL: Provide weak omap_rev_string omap: beagle: Use ubifs instead of jffs2 for nand boot omap: overo: Disable pull-ups on camera PCLK, HS and VS signals omap: overo: Configure mux for gpio10 SPL: Add DMA library omap3: Add interface for omap3 DMA omap3: Add DMA register accessors omap3: Add Base register for DMA arm, davinci: add missing LSPC define for MMC/SD1 U-Boot/SPL: omap4: Make ddr pre-calculated timings as default. DaVinci: correct MDSTAT.STATE mask omap4: splitting padconfs into common, 4430 and 4460 omap4: adding revision detection for 4460 ES1.1 omap4: replacing OMAP4_CONTROL with OMAP4430_CONTROL gplug: fixed build error as a result of code cleanup patch kirkwood_spi: add dummy spi_init() gpio: mvmfp: reduce include platform file ARM: orion5x: reduce dependence of including platform file serial: reduce include platform file for marvell chip ARM: kirkwood: reduce dependence of including platform file ARM: armada100: reduce dependence of including platform file ARM: pantheon: reduce dependence of including platform file Armada100: Add env storage support for Marvell gplugD Armada100: Add SPI flash support for Marvell gplugD Armada100: Add SPI support for Marvell gplugD SPI: Add SPI driver support for Marvell Armada100 dreamplug: initial board support. imx: fix coding style misc: pmic: drop old Freescale's pmic driver MX31: mx31pdk: use new pmic driver MX31: mx31ads: use new pmic driver MX31: mx31_litekit: use new pmic driver MX5: mx53evk: use new pmic driver MX5: mx51evk: use new pmic driver MX35: mx35pdk: use new pmic driver misc: pmic: addI2C support to pmic_fsl driver misc: pmic: use I2C_SET_BUS in pmic I2C MX5: efikamx/efikasb: use new pmic driver MX3: qong: use new pmic driver RTC: Switch mc13783 to generic pmic code MX5: vision2: use new pmic driver misc: pmic: Freescale PMIC switches to generic PMIC driver misc:pmic:samsung Enable PMIC driver at GONI target misc:pmic:max8998 MAX8998 support at a new PMIC driver. misc:pmic:core New generic PMIC driver mx31pdk: Remove unneeded config mx31: provide readable WEIM CS accessor MX51: vision2: Set global macros I2C: Add i2c_get/set_speed() to mxc_i2c.c ARM: Update mach-types devkit8000: Add config to enable SPL MMC boot devkit8000: protect board_mmc_init arm, post: add missing post_time_ms for arm cosmetic, post: Codingstyle cleanup arm, logbuffer: make it compileclean tegra2: Enable MMC for Seaboard tegra2: Add more pinmux functions tegra2: Rename PIN_ to PINGRP_ tegra2: Add more clock functions tegra2: Clean up board code a little tegra2: Rename CLOCK_PLL_ID to CLOCK_ID
| * mmc: omap: Allow OMAP_HSMMC[23]_BASE to be unsetTom Rini2011-10-27-0/+4
| | | | | | | | | | | | | | | | | | Not all omap families define OMAP_HSMMC[23]_BASE so condition those cases in omap_mmc_init(). Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| * tegra2: Enable MMC for SeaboardTom Warren2011-10-27-1/+1
| | | | | | | | | | | | | | | | This adds the required GPIO and pinmux configuration to make eMMC / SD work on Seaboard. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
| * tegra2: Add more clock functionsSimon Glass2011-10-27-61/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds most of the clock functions required by board and driver code: -query and adjust peripheral clocks -query and adjust PLLs -reset and enable control These functions are plumbed in as required. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
* | GCC4.6: Fix warnings in pxa_mmc.cMarek Vasut2011-10-27-16/+16
|/ | | | | | | | | | | | | | | | | | | | | | | | | pxa_mmc.c: In function 'mmc_cmd': pxa_mmc.c:77:2: warning: format '%08x' expects type 'unsigned int', but argument 2 has type 'ulong' pxa_mmc.c: In function 'mmc_block_read': pxa_mmc.c:110:2: warning: format '%d' expects type 'int', but argument 4 has type 'ulong' pxa_mmc.c: In function 'pxa_mmc_write': pxa_mmc.c:327:2: warning: format '%lx' expects type 'long unsigned int', but argument 2 has type 'uchar *' pxa_mmc.c:349:2: warning: format '%lx' expects type 'long unsigned int', but argument 2 has type 'uchar *' pxa_mmc.c:354:3: warning: format '%lx' expects type 'long unsigned int', but argument 2 has type 'uchar *' pxa_mmc.c:362:2: warning: format '%lx' expects type 'long unsigned int', but argument 2 has type 'uchar *' pxa_mmc.c:367:3: warning: format '%lx' expects type 'long unsigned int', but argument 2 has type 'uchar *' Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Mike Frysinger <vapier@gentoo.org>
* mmc: dcache: allocate cache aligned buffers for ext_csdAnton staaf2011-10-25-2/+2
| | | | | | | | | | | | | | | Currently the mmc_change_freq and mmc_startup functions allocates buffers on the stack that are passed down to the MMC device driver. These buffers could be unaligned to the L1 dcache line size. This causes problems when using DMA and with caches enabled. This patch correctly cache alignes the buffers used for reading the ext_csd data from an MMC device. Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* mmc: dcache: allocate cache aligned buffer for scr and switch_statusAnton staaf2011-10-25-5/+5
| | | | | | | | | | | | | | | | | Currently the sd_change_freq function allocates two buffers on the stack that it passes down to the MMC device driver. These buffers could be unaligned to the L1 dcache line size. This causes problems when using DMA and with caches enabled. This patch correctly cache alignes the buffers used for reading the scr register and switch status values from an MMC device. Change-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d Signed-off-by: Anton Staaf <robotboy@chromium.org> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mmc: omap: config VMMC, MMC1_PBIASBalaji T K2011-09-30-3/+28
| | | | | | | | | | Config VMMC voltage to 3V for MMC/SD card slot and PBIAS settings needed for OMAP4 Fixes MMC/SD detection on boot from eMMC. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mmc: omap: enable high capacityBalaji T K2011-09-30-1/+2
| | | | | | | | | | Enable high capacity to host capability. Fixes eMMC detection on boot from MMC/SD card. Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ftsdc010: add support of ftsdc010 mmc controllerMacpaul Lin2011-09-04-0/+668
| | | | | | Faraday FTSDC010 controller is a SD/MMC controller for SoC chip. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
* mmc: Fix mmc_send_status()Marek Vasut2011-09-04-1/+2
| | | | | | | | The mmc_send_status() function sets cmd.arg = 0. That's incorrect, so fix it. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Acked-by: Andy Fleming <afleming@freescale.com> Tested-by: Lei Wen <adrian.wenl@gmail.com>
* OMAP3: Remove legacy mmc driverTom Rini2011-09-04-804/+0
| | | | | | | | Now that all platforms have been migrated to the new MMC driver, remove the old one. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* mmc: S5P: Support DMA restarts at buffer boundariesAnton Staaf2011-09-03-4/+11
| | | | | | | | | | | | | | | | | | Currently if a DMA buffer straddles a buffer alignment boundary (512KiB) then the DMA engine will pause and generate a DMA interrupt. Since the DMA interrupt is not enabled it will hang the MMC driver. This patch adds support for restarting the DMA transfer. The SYSTEM_ADDRESS register contains the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf <robotboy@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Tested-by : Jaehoon Chung <jh80.chung@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Revert "AT91:mmc:fix multiple read/write error"Andy Fleming2011-07-28-12/+1
| | | | | | | | | This reverts commit c310fc840472a36e4b9d2505830e9dc8d458d63c. The Atmel custodian had apparently rejected this patch's approach in another thread, so this patch reverts it for now. Signed-off-by: Andy Fleming <afleming@freescale.com>
* disk/part.c: Make features optionalMatthew McClintock2011-07-26-0/+2
| | | | | | | | | If we don't want to build support for any partition types we can now add #undef CONFIG_PARTITIONS in a board config file to keep this from being compiled in. Otherwise boards assume this is compiled in by default Signed-off-by: Matthew McClintock <msm@freescale.com>
* AT91:mmc:fix multiple read/write errorelen.song2011-07-15-1/+12
| | | | | | | According to datasheet,set block count before multiple read/write. Signed-off-by: elen.song <elen.song@atmel.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mmc: Access mode validation for eMMC cards > 2 GiBŁukasz Majewski2011-07-15-2/+6
| | | | | | | | | | | | | | | | This patch provides handling of the two way handshake when SEND_OP_COND (CMD1) is send to mmc card. It is necessary to inform eMMC card if the host can work with high capacity cards (Jedec JESD84-A441, point 7.4.3). The extra flag MMC_MODE_HC (high capacity) is added to indicate if the host is capable of handling the high capacity eMMC cards. Since this change is added to the generic mmc framework, then it requires other boards to indicate if their mmc controllers can handle high capacity cards. As it is now - the old behaviour of the framework is preserved. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: sh_mmcif: add support for Renesas MMCIFYoshihiro Shimoda2011-07-15-0/+847
| | | | | | | Some Renesas SuperH have MMCIF module. This driver supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mmc: fix the condition for MMC version 4Yoshihiro Shimoda2011-07-15-4/+11
| | | | | | | | | | Fix the problem that if we use the chip of MMC version 4 and the capacity is smaller than 2GB or equal, the mmc->capacity is invalid. According to the JEDEC Standard, the value of ext_csd's capacity is valid if the value is more than 2GB. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add marvell sdhci driverLei Wen2011-07-15-0/+22
| | | | | | | | | This could support both armada100 and pantheon serial in the mainline, while this driver also be tested to support upcoming mg, mmp2 and mmp3 hardware. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add sdhci generic frameworkLei Wen2011-07-15-0/+434
| | | | | | | | | Nowdays, there are plenty of mmc driver in uboot adopt the sd standard host design, aka as sdhci. It is better to centralize the common logic together to better maintenance. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add erase function to both mmc and sdLei Wen2011-07-15-0/+102
| | | | | | | | | | | Erase is a very basic function since the begin of sd specification is announced. Although we could write a bulk of full 0xff memory to the range to take place of erase, it is more convenient and safe to implement the erase function itself. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mmc: Tegra2: SD/MMC driver for Seaboard - eMMC on SDMMC4, SDIO on SDMMC3Tom Warren2011-07-15-0/+592
| | | | | Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Andy Fleming <afleming@freescale.com>
* S5P: add set_mmc_clk for external clock controlJaehoon Chung2011-05-26-0/+4
| | | | | | | | | | | This patch added set_mmc_clk for external clock control. c210 didn't support host clock control. So We need external_clock_control function for c210. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* MMC S5P: Fix typoDirk Behme2011-05-26-1/+1
| | | | | | | | | | | | | | | Fix typo resulting in the compilation error s5p_mmc.c: In function 's5p_mmc_initialize': s5p_mmc.c:469: error: 'struct mmc' has no member named 'm_bmax' introduced by commit "MMC: make b_max unconditional" (8feafcc49c0b7a9c541904f95a43dbef2fecc38b) Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: John Rigby <john.rigby@linaro.org> CC: Andy Fleming <afleming@freescale.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Minor coding style cleanup.Wolfgang Denk2011-05-19-4/+4
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
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