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* mmc: sdhci: return error when failed add_sdhci().Jaehoon Chung2013-05-06-4/+2
| | | | | | | | | If failed the add_host(), it is reasonable that return value of add_sdhci(). Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* sdhci: Add sdhci support for spear devicesVipin Kumar2013-05-06-0/+45
| | | | | | | Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* davinci, mmc: Added a delay reading ext CSD registerDavide Bonfanti2013-05-06-1/+4
| | | | | | | | | | | | | | Without this additional delay, some eMMC don't negotiate properly bus width Tested on: - Toshiba THGBM2G8D8FBAIB - Toshiba THGBM4G4D1HBAR - Micron MTFC4GMVEA (the one giving the problem) - Hynix H26M64002BNR - SanDisk SDIN5E1-32G Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: Split device init to decouple OCR-polling delayChe-Liang Chiou2013-05-06-32/+105
| | | | | | | | | | | | | | | | | | | Most of time that MMC driver spends on initializing a device is polling OCR (operation conditions register). To decouple this polling loop, device init is split into two parts: The first part fires the OCR query command, and the second part polls the result. So the caller is now no longer bound to the OCR-polling delay; he may fire the query, go somewhere and then come back later for the result. To use this, call mmc_set_preinit() on any device which needs this. This can save significant amounts of time on boot (e.g. 200ms) by hiding the MMC init time behind other init. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* part/dev_desc: Add log2 of blocksize to block_dev_desc data structEgbert Eich2013-05-01-0/+1
| | | | | | | | | | log2 of the device block size serves as the shift value used to calculate the block number to read in file systems when implementing avaiable block sizes. It is needed quite often in file systems thus it is pre-calculated and stored in the block device descriptor. Signed-off-by: Egbert Eich <eich@suse.com>
* mmc: Define a constant for the maximum block sizeSimon Glass2013-05-01-12/+13
| | | | | | | | | The number 512 appears quite a bit in the mmc code. Add a constant for this so that it can be used here and in other parts of the code (e.g. SPL code which loads from mmc). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* spl_mmc: cleanup variable typesPeter Korsgaard2013-05-01-8/+9
| | | | | | | | | | | block_read returns unsigned long, so it doesn't make sense to check for < 0. and neither does marking the header structure as const and then casting away the constness to load data into it. Also cleanup some unneeded pointer casting while we're at it. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> Reviewed-by: Tom Rini <trini@ti.com>
* mmc: check the revision for sd3.0Jaehoon Chung2013-04-17-0/+2
| | | | | | | | Support to check whether the SD3.0 or not. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Rommel Custodio <sessyargc@gmail.com>
* mmc: support the correct card version for eMMCJaehoon Chung2013-04-17-0/+18
| | | | | | | | | | | eMMC vesrion is supported up to v4.5. But bootloader isn't saw the exact eMMC version. After applied this patch, if use the mmcinfo command, then can see the exactly mmc version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rommel Custodio <sessyargc@gmail.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-5/+3
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| * fsl_esdhc: Fix DMA transfer completion waiting loopAndrew Gabbasov2013-04-14-2/+1
| | | | | | | | | | | | | | | | | | | | | | Rework the waiting for transfer completion loop condition to continue waiting until both Transfer Complete and DMA End interrupts occur. Checking of DLA bit in Present State register looks not needed in addition to interrupts status checking, so it can be removed from the condition. Also, DMA Error condition is added to the list of data errors, checked in the loop. Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
| * fsl_esdhc: flush cache after IO completionEric Nelson2013-04-14-3/+2
| | | | | | | | | | | | | | | | | | The cache should invalidate the read buffer for the SD card interface after the transfer complete, not command-complete. Tested-by: Andrew Gabbasov <Andrew_Gabbasov@mentor.com> Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
* | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-04-0/+7
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| * mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a boardAbbas Raza2013-04-03-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Maximum bus width supported by some i.MX6 boards is not 8bit like others. In case where both host controller and card support 8bit transfers, they agree to communicate on 8bit interface while some boards support only 4bit interface. Due to this reason the mmc 8bit default mode fails on these boards. To rectify this, define maximum bus width supported by these boards (4bit). If max_bus_width is not defined, it is 0 by default and 8bit width support will be enabled in host capabilities otherwise host capabilities are modified accordingly. It is tested with a MMCplus card. Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com> cc: stefano Babic <sbabic@denx.de> cc: Andy Fleming <afleming@gmail.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
* | ARM: bcm2835: fix get_timer() to return msStephen Warren2013-04-04-2/+3
| | | | | | | | | | | | | | | | | | | | Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-26-3/+5
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| * | mmc:sdhci:fix: Change default interrupts enabled at SDHCI initializationŁukasz Majewski2013-03-12-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes sdhci_init()'s behavior to NOT enable all interrupt sources by default. Moreover interrupt signaling has been disabled. This patch do not enable interrupts which aren't served in u-boot (they are defined at sdhci.h but NOT used elsewhere): - SDHCI_INT_CARD_INSERT, SDHCI_INT_CARD_REMOVE, SDHCI_BUS_POWER, SDHCI_INT_CARD_REMOVE, SDHCI_INT_CARD_INT Special care shall be put on SDHCI_INT_CARD_INT, which indicates interrupt generated by SD card. According to "SD Host Controller Simplified Spec. ver 3.00" when bit 8 (Card Interrupt Status Enable) at "Normal Interrupt Status Enable Register" (offset 0x34) is set, the card interrupt detection is started. Then eMMC card may cause the SD controller to set this bit and then this interrupt is passed to booted OS and might cause kernel crash. To sum up: - Only enable interrupts, which are served at u-boot - This cleanup as a side effect fixes SDHCI's CARD INTERRUPT problem at Linux kernel (versions 3.6+, sdhci controller) - Keep masked bits at "Normal Interrupt Signal Enable Register" (0x38h) Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lei Wen <leiwen@marvell.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | mmc: omap_hsmmc.c: only register getcd/getwp callbacks if gpio could be usedPeter Korsgaard2013-03-24-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Gets rid of warnings from omap_gpio: ERROR : check_gpio: invalid GPIO -1 (and undefined behaviour as the -1 error code is interpreted as gpio value) Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
* | | mmc: mmc_getcd/getwp: use sensible defaultsPeter Korsgaard2013-03-24-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Let mmc_getcd() return true and mmc_getwp() false if mmc driver doesn't provide handlers for them. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Add braces around first if test in each case to fix warning] Signed-off-by: Tom Rini <trini@ti.com>
* | | mmc: add bcm2835 driverStephen Warren2013-03-20-0/+190
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple driver for the BCM2835's SD controller. Workarounds are implemented for: * Register writes can't be too close to each-other in time, or they will be lost. * Register accesses must all be 32-bit, so implement custom accessors. This code was extracted from: git://github.com/gonzoua/u-boot-pi.git master which was created by Oleksandr Tymoshenko. Portions of the code there were obviously based on the Linux kernel at: git://github.com/raspberrypi/linux.git rpi-3.6.y commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley. swarren changed the following for upstream: * Removed hack udelay()s in bcm2835_sdhci_raw_writel(); setting SDHCI_QUIRK_WAIT_SEND_CMD appears to solve the issues. * Remove register logging from read*/write* functions. * Sort out confusion with min/max_freq values passed to add_sdhci(). * Use more descriptive variable names and calculations in IO accessors. * Simplified and commented twoticks_delay calculation. * checkpatch fixes. Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Acked-by: Andy Fleming <afleming@gmail.com>
* | Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-58/+168
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| * | mmc: Tegra: Add SD bus power/voltage function and MMC pad init call.Tom Warren2013-03-14-8/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra30 requires the SD Bus Voltage & Power bits be set in the SD Power Control register. Tegra20 works w/o them set, but do it anyway for those SoCs as it's part of the SD spec. Also call a common board pad init routine (pad_init_mmc) in mmc_reset(), used by Tegra30 only for now. Note that Tegra20 SD/MMC HW differs enough from Tegra20 that a new compatible entry is used in the fdt compat_names/id tables. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * | Tegra: MMC: Add DT support to MMC driver for all T20 boardsTom Warren2013-03-14-58/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc. Tested on Seaboard, fully functional. Tamonten boards (medcom-wide, plutux, and tec) use a different/new dtsi file w/common settings. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* | | Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-03-15-16/+4
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| * | mxs: mmc: spi: dma: Better wrap the MXS differencesMarek Vasut2013-03-07-16/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch streamlines the differences between the MX23 and MX28 by implementing a few helper functions to handle different DMA channel mapping, different clock domain for SSP block and fixes a few minor bugs. First of all, the DMA channel mapping is now fixed in dma.h by defining the actual channel map for both MX23 and MX28. Thus, MX23 now does no longer use MX28 channel map which was wrong. Also, there is a fix for MX28 DMA channel map, where the last four channels were incorrect. Next, because correct DMA channel map is in place, the mxs_dma_init_channel() call now bases the channel ID starting from SSP port #0. This removes the need for DMA channel offset being added and cleans up the code. For the same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus no need to adjust dma channel number in the driver either. Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus() which handles the fact that MX23 has shared SSP clock for both ports, while MX28 has per-port SSP clock. Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the same functionality from MMC and SPI driver into common code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
* | Merge u-boot/master into u-boot-ti/masterTom Rini2013-03-11-16/+52
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In master we had already taken a patch to fix the davinci GPIO code for CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850). Resolve these conflicts manually and comment the #else/#endif lines for clarity. Conflicts: arch/arm/include/asm/arch-davinci/gpio.h drivers/gpio/da8xx_gpio.c Signed-off-by: Tom Rini <trini@ti.com>
| * | blackfin: bf60x: add rsi/sdh supportSonic Zhang2013-03-04-16/+52
| |/ | | | | | | | | | | | | | | Add rsi/sdh support for bf60x. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com> Signed-off-by: Sonic Zhang <sonic.adi@gmail.com>
* | ARM: OMAP4+: Make control module register structure genericLokesh Vutla2013-03-11-15/+10
| | | | | | | | | | | | | | | | | | | | | | | | A seperate omap_sys_ctrl_regs structure is defined for omap4 & 5. If there is any change in control module for any of the ES versions, a new structure needs to be created. In order to remove this dependency, making the register structure generic for all the omap4+ boards. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
* | omap_hsmmc: add driver check for write protectionNikita Kiryanov2013-03-08-2/+12
| | | | | | | | | | | | | | | | Add check for write protection in omap mmc driver. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Reviewed-by: Tom Rini <trini@ti.com>
* | mmc: add support for write protectionNikita Kiryanov2013-03-08-0/+30
| | | | | | | | | | | | | | Add generic mmc write protection functionality. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | omap_hsmmc: implement driver check for card detectionNikita Kiryanov2013-03-08-2/+35
| | | | | | | | | | | | | | Implement driver check for card detection. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* | omap_hsmmc: introduce omap_hsmmc_data structNikita Kiryanov2013-03-08-10/+18
| | | | | | | | | | | | | | | | | | | | Currently there's no appropriate place to store driver specific data because the pointer that is meant for that (priv) is being used to store the base address of mmc registers. Introduce a new struct for storing driver specific data. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | omap_hsmmc: fix out of bounds array accessNikita Kiryanov2013-03-08-1/+1
|/ | | | | | | | | | There are 3 MMC/SD/SDIO controllers in OMAP SoCs, but only 2 structs are defined for devices. This leads to data being written outside of array bounds on systems that use all 3 controllers. Update hsmmc_dev array to the correct size. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-02-12-41/+61
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| * mxs: mmc: Fix the MMC driver for MX23Marek Vasut2013-01-28-5/+22
| | | | | | | | | | | | | | | | | | | | The MX23 has different layout of DMA channels. Fix the MMC driver to support MX23. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: mmc: Allow overriding default card detect implementationMarek Vasut2013-01-28-2/+14
| | | | | | | | | | | | | | | | | | | | Some MXS based boards do not implement the card-detect signal. Allow user to specify alternate card-detect implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: mmc: Fix MMC reset on iMX23Otavio Salvador2013-01-28-5/+11
| | | | | | | | | | | | | | | | | | | | This does the same reset mask as done in v3.7 Linux kernel code. The block is properly configured for MMC operation that way. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mmc: Limit the number of used SSP ports on MX23Marek Vasut2013-01-21-1/+11
| | | | | | | | | | | | | | | | | | | | The MX23 can only use two SSP ports. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: clock: Use 'mxs' prefix for methodsOtavio Salvador2013-01-21-2/+2
| | | | | | | | | | | | | | Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: ssp: Pull out the SSP bus to regs conversionMarek Vasut2013-01-21-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Create function which converts SSP bus number to SSP register pointer. This functionality is reimplemented multiple times in the code, thus make one common implementation. Moreover, make it a switch(), since the SSP ports are not mapped in such nice linear fashion on MX23, therefore having it a switch will simplify things there. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * mxs: mmc: Drop unused members from struct mxsmmc_privMarek Vasut2013-01-21-12/+0
| | | | | | | | | | | | | | | | | | The clock data are not used by the driver, drop them. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | ppc: arm: Move sdhc_clk into arch_global_dataSimon Glass2013-02-04-3/+3
|/ | | | | | | This is used by both powerpc and arm, but I think it still qualifies as architecture-specific. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-01-08-1/+1
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| * fsl_esdhc: add MMC_MODE_HC host_capsShawn Guo2013-01-05-1/+1
| | | | | | | | | | | | | | | | All esdhc variants we know should support high capacity MMC cards, so let's add MMC_MODE_HC host_caps unconditionally to support those MMC cards (capacity > 2 GB). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge branch 'master' of git://git.denx.de/u-boot into resolveMinkyu Kang2012-12-10-65/+153
|\ \ | |/ | | | | | | | | | | | | | | | | | | Conflicts: README board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| * mmc: Properly determine maximum supported bus widthAndy Fleming2012-11-27-12/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At some point, a confusion arose about the use of the bit definitions in host_caps for bus widths, and the value in ext_csd. By coincidence, a simple shift could convert between one and the other: MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0 MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1 MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2 However, as host_caps is a bitmask of supported things, there is not, in fact, a one-to-one correspondence. host_caps is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical things were happening where we would try to set the bus width to 12. The new code clarifies the very different namespaces: host_caps/card_caps = bitmask (MMC_MODE_*) ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*) mmc->bus_width integer number of bits (1, 4, 8) We create arrays to map between the namespaces, like in Linux. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Stephen Warren <swarren@nvidia.com>
| * mmc: tegra: use bounce buffer APIsStephen Warren2012-11-27-23/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * common: rework bouncebuf implementationStephen Warren2012-11-27-23/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current bouncebuf API requires all parameters to be passed to both bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf start function to accept a state structure as a parameter, and only require that state struct to be passed to the stop function. This simplifies usage of the bounce buffer by clients. Don't modify the data pointer, but rather store the temporary buffer in this state struct. The bouncebuf code ensures that client code can always use a single buffer pointer in the state structure, irrespective of whether a bounce buffer actually had to be allocated. Move cache management logic into the bounce buffer code, so that each client doesn't have to duplicate this. I believe there's no need to invalidate the buffer before a DMA operation, since flushing the cache should prevent any write-backs. Update the MXS MMC driver for this change. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: add no simultaenous power and vddMela Custodio2012-11-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in the code from Linux kernel. Added to Linux kernel by: commit e08c1694d9e2138204f2b79b73f0f159074ce2f5 Author: Andres Salomon <dilinger@queued.net> Date: Fri Jul 4 10:00:03 2008 -0700 Some HW balks when writing both voltage setting and power up at the same time to SDHCI_POWER_CONTROL register. Signed-off-by: Rommel G Custodio <sessyargc@gmail.com> CC: Andy Fleming <afleming@freescale.com> v2: fix attribution and SOB Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mmc: Fix interpretation of MMC_CMD_ALL_SEND_CIDTaylor Hutt2012-11-27-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | The interpretation of the data returned by the MMC_CMD_ALL_SEND_CID command was incorrect with respect to the JEDEC Standard No. 84-A441. This change makes the interpretation correct with respect to the defined fields of the CID register. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Taylor Hutt <thutt@chromium.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
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