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* mmc: add Faraday FTSDC021 SDHCI controller supportKuo-Jung Su2013-12-08-0/+34
| | | | | | | | | | | Faraday FTSDC021 is a controller which is compliant with SDHCI v3.0, SDIO v2.0 and MMC v4.3. However this driver is only verified with SD memory cards. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> CC: Andy Fleming <afleming@gmail.com>
* powerpc: mmc: Add corenet devices support in esdhc splPriyanka Jain2013-12-08-0/+5
| | | | | | | | | | | | | | | Existing eSDHC SPL framework assumes booting from sd-image with boot_format header which contains final u-boot Image offset and size. No such header is present in case of corenet devices like T1040 as corenet deivces use PBI-RCW based intialization. So, for corenet deives, SPL bootloader use values provided at compilation time. These values can be defined in board specific config file. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc/dwmmc: modify FIFO threshold only if value explicitly setAlexey Brodkin2013-12-08-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | If platform provides "host->fifoth_val" it will be used for initialization of DWMCI_FIFOTH register. Otherwise default value will be used. This implementation allows: * escape unclear and recursive calculations that are currently in use * use whatever custom value for DWMCI_FIFOTH initialization if any particular SoC requires it Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Alim Akhtar <alim.akhtar@samsung.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Andy Fleming <afleming@freescale.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: dw_mmc: remove the exynos specific code in dw-mmc.cJaehoon Chung2013-12-08-10/+16
| | | | | | | | | | | dw-mmc.c is the general driver file. So, remove the exynos specific code at dw-mmc.c. Instead, exynos specific cod can be move into exynos-dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* drivers: convert makefiles to Kbuild styleMasahiro Yamada2013-10-31-47/+24
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/esdhc: Add 3.3v voltage support in esdhc capacity registerHaijun.Zhang2013-10-31-0/+6
| | | | | | | | | | T4240QDS eSDHC host capabilities reigster should have VS33 bit define. Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity missing Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* esdhc: memset mmc struct before putting into useHaijun.Zhang2013-10-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct mmc should be clear to all '0' after malloc to avoid unexpect variable value. Like mmc->has_init = xxx. In this case mmcinfo will believe the card had been initialized before and skip the initialization. Test on P5040 and T4240, Error Log: => mmcinfo Device: FSL_SDHC Manufacturer ID: 0 OEM: 0 Name: Tran Speed: 0 Rd Block Len: 0 MMC version 0.0 High Capacity: No Capacity: 0 Bytes Bus Width: 0-bit => Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Xie Shaohui-B21989 <B21989@freescale.com> Tested-by: Ryan Barnett <rjbarnet@rockwellcollins.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Powerpc/esdhc: Add simple description of esdhc registerHaijun.Zhang2013-10-31-37/+37
| | | | | | | Add some descriptions for esdhc register for easily using. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* powerpc/esdhc: Map register for eSDHC Host Controller V3.0Haijun.Zhang2013-10-31-2/+14
| | | | | | | | | eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* DWMMC: SMDK5420: Disable SMU for eMMCRajeshwari Shinde2013-10-31-0/+14
| | | | | | | | | | | | SMDK5420 has a new Security Management Unit added for dwmmc driver, hence, configuring the control registers to support booting via eMMC. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: sdhci: Avoid commands errors by simple timeout adaptation.Przemyslaw Marczak2013-10-31-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | Old command timeout value was too small and it caused I/O errors which led to uncompleted read/write/erase operations and filesystem errors. Timeout adaptation fixes this issue. Changes in sdhci_send_command() function: - change timeout variable to static - increase default command timeout to 100 ms - add definition of max command timeout value, which can be redefined in each board config file - wait for card ready state for max defined time if it doesn't exceed defined maximum or return COMM_ERR Once successfully increased timeout value will be used in next function call. This fix was tested on Goni, Trats, Trats2 boards by testing UMS on MMC storage. Changes v2: - move global variable cmd_timeout into function sdhci_send_command() - change condition "==" to ">=" when comparing time with timeout - print information about timeout increasing and card busy timeout Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: dw_mmc: change the callback function name.Jaehoon Chung2013-10-31-4/+4
| | | | | | | | To prevent the confusion, use the get_mmc_clk() instead of mmc_clk(). get_mmc_clk() is more exactly name. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* mmc: Fix erase_grp_size for partitioned cardOliver Metz2013-10-31-4/+13
| | | | | | | | EXT_CSD_ERASE_GROUP_DEF is lost every time after a reset or power off. Set it if device has enhanced partitions. Signed-off-by: Oliver Metz <oliver@freetz.org> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-10-02-0/+2
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| * mmc: fsl_esdhc: Check the result from malloc()Fabio Estevam2013-09-20-0/+2
| | | | | | | | | | | | malloc can fail, so we should better check its return value before using it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* | Fix wrong sdhci host control register read and writeJuhyun \(Justin\) Oh2013-09-20-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes the improper read and write of sdhci host control register for sdma transfer. The problem comes when reading and writing 1 byte long host control register with the sdhci_readl() and sdhci_writel(). The misuse of these functions overwrite the value of the next registers which are in 4 bytes boundary. This patch replaces four byte register read/write functions with one byte read/write ones. Beside, it eliminates unnecessary bit operation. i.e. or-ing zero against a variable. Signed-off-by: Juhyun (Justin) Oh <Juhyun_Oh@sigmadesigns.com>
* | mmc/dw_mmc: Allocate the correct amount of descriptorsMischa Jonker2013-09-20-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes two issues: * a descriptor was allocated for every block, while a descriptor can take 8 blocks * there was an off-by-one error in the descriptor preparation: there were two last descriptors, one with length==0 Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Andy Fleming <afleming@gmail.com>
* | mmc/dw_mmc: Fix DMA descriptor corruptionMischa Jonker2013-09-20-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In dwmci_prepare_data, the descriptors are allocated for DMA transfer. These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses the stack to allocate these descriptors. This becomes a problem if the DMA transfer continues after the processor leaves the function in which the descriptors were allocated. Therefore, I have moved the allocated of the buffers up one level, to dwmci_send_cmd(). The DMA transfer should be complete when leaving this function. Signed-off-by: Mischa Jonker <mjonker@synopsys.com> Cc: Alexey Brodkin <abrodkin@synopsys.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Andy Fleming <afleming@gmail.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | mmc: don't support write & erase for SPL buildsPaul Burton2013-09-20-182/+230
| | | | | | | | | | | | | | | | | | | | For SPL builds this is just dead code since we'll only need to read. Eliminating it results in a significant size reduction for the SPL binary, which may be critical for certain platforms where the binary size is highly constrained. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | mmc: don't call *printf or puts when SPL & !CONFIG_SPL_LIBCOMMON_SUPPORTPaul Burton2013-09-17-0/+36
| | | | | | | | | | | | | | | | If we don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio & *printf functions are unavailable & calling them will cause a link failure. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
* | ARM: OMAP: Enable 8-bit eMMC access for OMAP4/5/DRA7xxLubomir Popov2013-09-17-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT (for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be defined in the board header if an 8-bit eMMC device is connected to the corresponding port. Fix the "No status update" error that appeared for eMMC devices by inserting a 20 us delay between writing arguments and command. This solution has been proposed by Michael Cashwell <mboards@prograde.net>. A minor cosmetic fix in a comment as well. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
* | omap_hsmmc: omap4+/am335x: modify MMC controller internal fsm reset funcOleksandr Tyshchenko2013-09-17-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "mmc_send_cmd: timeout: No status update" error sometimes happens in omap_hsmmc driver func mmc_send_cmd() when the MMC controller card identification and selection sequence is executed for eMMC on OMAP4 boards. It happens due to incorrect execution of CMD line reset procedure for OMAP4. Because CMD(DAT) lines reset procedures are slightly different for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx). According to OMAP3 TRM: Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it returns to 0x0. According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset procedure steps must be as follows: 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in MMCHS_SYSCTL register (SD_SYSCTL for AM335x). 2. Poll the SRC(SRD) bit until it is set to 0x1. 3. Wait until the SRC(SRD) bit returns to 0x0 (reset procedure is completed). Unfortunately, at present omap_hsmmc driver has support only for OMAP3. And as result step #2 is missing for OMAP4(AM335x,OMAP5,DRA7xx). This sometimes leads to the fact that the waiting loop which is required in step #3 does not executed, because SRC bit does not set yet (at the moment of checking a condition of a loop execution). And as a result this can cause to timeout error when sending a next command. In the particular case (working with eMMC witch do not respond to some SD specific command) due to incorrect reset sequence after command SD_CMD_SEND_IF_COND which finished with CTO flag within 64 clock cycles, the next command MMC_CMD_APP_CMD leads to a timeout error within 1s. So, extend CMD(DATA) lines reset procedure in func mmc_reset_controller_fsm() by adding the missing step #2 for OMAP4+/AM335x boards. Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | mmc: Remove unused variable backup from mmc_send_cmd()Oleksandr Tyshchenko2013-09-17-3/+0
| | | | | | | | | | | | | | | | Do not call a memset for unused variable backup every time. Remove unused variable from function. Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@ti.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* | mmc: sdhci: use the SDHCI_QUIRK_USE_WIDE8 for samsung SoCJaehoon Chung2013-09-17-7/+10
|/ | | | | | | | | Samsung SoC is supported the WIDE8, even if Controller version is v2.0. So add the SDHCI_QUIRK_USE_WIDE8 for Samsung-SoC. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-09-05-1/+2
|\ | | | | | | | | | | | | | | Conflicts: drivers/serial/serial.c The conflict above was a trivial case of adding one init function in each branch, and manually resolved in merge.
| * mmc: mxsmmc: Enable MMC HC supportAmaury Pouly2013-08-23-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for high-capacity eMMC and MMC cards. The MXS MMC driver has no problem with those. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Amaury Pouly <amaury.pouly@gmail.com> Cc: Andy Fleming <afleming@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Otavio Salvador <otavio@ossystems.com.br>
* | SPDX-License-Identifier: clean up license headerYork Sun2013-08-20-16/+1
| | | | | | | | | | | | | | | | | | This patch cleans up license header in these files: board/freescale/p1022ds/spl.c drivers/mmc/fsl_esdhc_spl.c drivers/mtd/spi/fsl_espi_spl.c Signed-off-by: York Sun <yorksun@freescale.com>
* | powerpc: mpc85xx: Support booting from SD Card with SPLYing Zhang2013-08-20-0/+135
|/ | | | | | | | | | | | | | | | The code from the internal on-chip ROM. It loads the final uboot image into DDR, then jump to it to begin execution. The SPL's size is sizeable, the maximum size must not exceed the size of L2 SRAM. It initializes the DDR through SPD code, and copys final uboot image to DDR. So there are two stage uboot images: * spl_boot, 96KB size. The env variables are copied to L2 SRAM, so that ddr spd code can get the interleaving mode setting in env. It loads final uboot image from offset 96KB. * final uboot image, size is variable depends on the functions enabled. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-nds32Tom Rini2013-07-25-1/+5
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| * mmc: ftsdc010_mci: fix build error if CONFIG_FTSDC010_SDIO is not definedGabor Juhos2013-07-24-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FTSDC010_DCR_FIFO_RST symbol is conditionally defined in <faraday/ftsdc010.h> and it is available available when CONFIG_FTSDC010_SDIO is enabled. However the actual driver code unconditionally uses the FTSDC010_DCR_FIFO_RST constant and this causes build error if CONFIG_FTSDC010_SDIO is not enabled. The following error happens when compiling for the adp-ag101 board: ftsdc010_mci.c: In function 'ftsdc010_request': ftsdc010_mci.c:178: error: 'FTSDC010_DCR_FIFO_RST' undeclared (first use in this function) ftsdc010_mci.c:178: error: (Each undeclared identifier is reported only once ftsdc010_mci.c:178: error: for each function it appears in.) The patch ensures that the FTSDC010_DCR_FIFO_RST symbol gets used only if CONFIG_FTSDC010_SDIO is defined. Compile tested only. Cc: Kuo-Jung Su <dantesu@faraday-tech.com> Cc: Macpaul Lin <macpaul@andestech.com> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Reviewed-by: Kuo-Jung Su <dantesu@faraday-tech.com>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-234/+17
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* fsl_esdhc: Touch only relevant sys ctrl bitsDirk Behme2013-07-16-3/+3
| | | | | | | | | | | | | Dealing with the sys ctrl register should touch only the relevant bits and not accidently the whole register. On i.MX6, the sys control register contains bits which shouldn't be reset to 0, e.g. SYS_CTRL[3-0] and IPP_RST_N (SYS_CTRL[23]). Do this by read/modify/write instead of just a 32bit write. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Andy Fleming <afleming@freescale.com>
* drivers/mmc/dw_mmc - remove extra arch specific "asm/arch/clk.h" inclusionAlexey Brodkin2013-07-16-1/+0
| | | | | | | | | | | | | | | | | | 1. No contents of "asm/arch/clk.h" is used within "dw_mmc.c". 2. If arch doesn't have "asm/arch/clk.h" driver won't build. Without mentioned inclusion dw_mmc driver could be built for arches other than ARM. For ARM driver still builds without it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com> Cc: Amar <amarendra.xt@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Powerpc: eSDHC: Fix mmc read write err in uboot of T4240QDS boardHaijun.Zhang2013-07-16-1/+1
| | | | | | | | | Fill the right command type when using CMD12 to stop data transfer. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fix block device accesses beyond 2TiBSascha Silbe2013-06-26-8/+9
| | | | | | | | | | | | | | | | | | With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type, which is required to represent block numbers for storage devices that exceed 2TiB (the block size usually is 512B), e.g. recent hard drives. For some obscure reason, the current U-Boot code uses lbaint_t for the number of blocks to read (a rather optimistic estimation of how RAM sizes will evolve), but not for the starting address. Trying to access blocks beyond the 2TiB boundary will simply wrap around and read a block within the 0..2TiB range. We now use lbaint_t for block start addresses, too. This required changes to all block drivers as the signature of block_read(), block_write() and block_erase() in block_dev_desc_t changed. Signed-off-by: Sascha Silbe <t-uboot@infra-silbe.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2013-06-22-23/+265
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| * Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2013-06-19-23/+265
| |\ | | | | | | | | | | | | Conflicts: spl/Makefile
| | * MMC: DWMMC: Fix FIFO_DEPTH calculationRajeshwari Shinde2013-06-17-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current DWMMC driver used to give FIFO underrun/overrun error every 3rd time for mmc rescan command. In current code FIFO_DEPTH is getting calculated after reading the default FIFOTH register and extracting the RX_WMARK bits from it i.e (RX_WMARK = FIFO_DEPTH/2 -1). Instead of storing the correct value, we were recalculating the FIFO_DEPT each time which is not correct. Based on "[PATCH V9 3/9] DWMMC: Initialise dwmci and resolve EMMC read write issues" http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/160247 Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * MMC: APIs to support resize of EMMC boot partitionAmar2013-06-13-0/+134
| | | | | | | | | | | | | | | | | | | | | This patch adds APIs to access(open / close) and to resize boot partiton of EMMC. Signed-off-by: Amar <amarendra.xt@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * EXYNOS5: DWMMC: Added FDT support for DWMMCAmar2013-06-13-10/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds FDT support for DWMMC, by reading the DWMMC node data from the device tree and initialising DWMMC channels as per data obtained from the node. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * DWMMC: Initialise dwmci and resolve EMMC read write issuesAmar2013-06-13-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enumerates dwmci and set auto stop command during dwmci initialisation. EMMC read/write is not happening in current implementation due to improper fifo size computation. Hence modified the fifo size computation to resolve EMMC read write issues. Signed-off-by: Amar <amarendra.xt@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-mmcTom Rini2013-06-14-17/+74
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| * | mmc: report capacity for the selected partitionStephen Warren2013-06-13-7/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhance the MMC core to calculate the size of each MMC partition, and update mmc->capacity whenever a partition is selected. This causes: mmc dev 0 1 ; mmcinfo ... to report the size of the currently selected partition, rather than always reporting the size of the user partition. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | fsl_esdhc: Do not clear interrupt status bits until data processedAndrew Gabbasov2013-06-13-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After waiting for the command completion event, the interrupt status bits, that occured to be set by that time, are cleared by writing them back. It is supposed, that it should be command related bits (command complete and may be command errors). However, in some cases the DMA already completes by that time before the full transaction completes. The corresponding DINT bit gets set and then cleared before even entering the loop, waiting for data part completion. That waiting loop never gets this bit set, causing the operation to hang. This is reported to happen, for example, for write operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II 8GB card. The solution could be to explicitly clear only command related interrupt status bits. However, since subsequent processing does not rely on any command bits state, it could be easier just to remove clearing of any bits at that point, leaving them all until all data processing completes. After that the whole register will be cleared at once. Also, on occasion, interrupts masking moved to before writing the command, just for the case there should be no chance of interrupt between the first command and interrupts masking. Reported-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | mmc: fsl_esdhc: Fix hang after 'save' commandFabio Estevam2013-06-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 48e0b2bd (powerpc/esdhc: Correct judgement for DATA PIO mode) we see mx6 systems to hang after doing a 'save' command. Revert this commit since the original 'ifdef' logic from 7b43db92 (drivers/mmc/fsl_esdhc.c: fix compiler warnings) was the correct one. Reported-by: Tapani Utriainen <tapani@technexion.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | mmc write bug fixRuud Commandeur2013-06-13-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bug related to mmc writes. When doing fatwrites on an SD-Card, MMC bus problems can occur. Depending on the size of the file, "MMC0: Bus busy timeout!" is reported, resulting in an SD-Card that is no longer responding. It appears to be, that set_cluster can be called with a size being zero. That can be with a file that has a size being an exact multiple (including 0) of the clustersize, but also for files that are smaller than the size of one cluster. The same problem occurs if the "mmc write" command is given with a block count being 0. By adding a check for the block count being zero in mmc_write_blocks (drivers/mmc.c), this problem is solved. Signed-off-by: Ruud Commandeur <rcommandeur@clb.nl> Cc: Tom Rini <trini@ti.com> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Mats Karrman <Mats.Karrman@tritech.se> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | mmc: sdhci: Enable 8-bit bus width only for 3.0 spec onwardsJagannadha Sutradharudu Teki2013-06-13-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAP register don't have any information for 8-bit buswidth support on 2.0 sdhci spec, only from 3.0 onwards bit[18] got this information. Due to this misassignment in sdhci, mmc is setting 8-bit buswidth using mmc_set_bus_width even if controller doesn't support. Below change has code information. "mmc: Properly determine maximum supported bus width" (sha1: 7798f6dbd5e1a3030ed81a81da5dfb57c3307cac) Bug log: <mmc plus and emmc cards) ------- zynq-uboot> mmcinfo Error detected in status(0x208100)! Device: zynq_sdhci Manufacturer ID: fe ..... So enable 8-bit support only for 3.0 spec using CAP and for below 3.0 assign mmc->host_caps = MMC_MODE_8BIT on respective platform driver if host have a support. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | mmc: omap_hsmmc: Update pbias programmingBalaji T K2013-06-10-11/+9
|/ / | | | | | | | | | | | | Update pbias programming sequence for OMAP5 ES2.0/DRA7 Signed-off-by: Balaji T K <balajitk@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-30-868/+536
|\ \ | |/ |/| | | | | | | Conflicts: common/cmd_fpga.c drivers/usb/host/ohci-at91.c
| * powerpc/esdhc: Correct judgement for DATA PIO modeHaijun.Zhang2013-05-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The logic for the whether to configure for polling or DMA was mistakenly reversed in this patch: Commit 7b43db92110ec2f15c5f7187a165f2928464966b drivers/mmc/fsl_esdhc.c: fix compiler warnings Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> CC: Sun Yusong-R58495 <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
generated by cgit v1.1 at 2024-11-10 00:34:14 +0000