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* mmc: S5P: Support DMA restarts at buffer boundariesAnton Staaf2011-09-03-4/+11
| | | | | | | | | | | | | | | | | | Currently if a DMA buffer straddles a buffer alignment boundary (512KiB) then the DMA engine will pause and generate a DMA interrupt. Since the DMA interrupt is not enabled it will hang the MMC driver. This patch adds support for restarting the DMA transfer. The SYSTEM_ADDRESS register contains the next address that would have been read/written when a boundary is hit. So we can read that and write it back. The write triggers the resumption of the transfer. Signed-off-by: Anton Staaf <robotboy@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Tested-by : Jaehoon Chung <jh80.chung@samsung.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* Revert "AT91:mmc:fix multiple read/write error"Andy Fleming2011-07-28-12/+1
| | | | | | | | | This reverts commit c310fc840472a36e4b9d2505830e9dc8d458d63c. The Atmel custodian had apparently rejected this patch's approach in another thread, so this patch reverts it for now. Signed-off-by: Andy Fleming <afleming@freescale.com>
* disk/part.c: Make features optionalMatthew McClintock2011-07-26-0/+2
| | | | | | | | | If we don't want to build support for any partition types we can now add #undef CONFIG_PARTITIONS in a board config file to keep this from being compiled in. Otherwise boards assume this is compiled in by default Signed-off-by: Matthew McClintock <msm@freescale.com>
* AT91:mmc:fix multiple read/write errorelen.song2011-07-15-1/+12
| | | | | | | According to datasheet,set block count before multiple read/write. Signed-off-by: elen.song <elen.song@atmel.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mmc: Access mode validation for eMMC cards > 2 GiBŁukasz Majewski2011-07-15-2/+6
| | | | | | | | | | | | | | | | This patch provides handling of the two way handshake when SEND_OP_COND (CMD1) is send to mmc card. It is necessary to inform eMMC card if the host can work with high capacity cards (Jedec JESD84-A441, point 7.4.3). The extra flag MMC_MODE_HC (high capacity) is added to indicate if the host is capable of handling the high capacity eMMC cards. Since this change is added to the generic mmc framework, then it requires other boards to indicate if their mmc controllers can handle high capacity cards. As it is now - the old behaviour of the framework is preserved. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: sh_mmcif: add support for Renesas MMCIFYoshihiro Shimoda2011-07-15-0/+847
| | | | | | | Some Renesas SuperH have MMCIF module. This driver supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mmc: fix the condition for MMC version 4Yoshihiro Shimoda2011-07-15-4/+11
| | | | | | | | | | Fix the problem that if we use the chip of MMC version 4 and the capacity is smaller than 2GB or equal, the mmc->capacity is invalid. According to the JEDEC Standard, the value of ext_csd's capacity is valid if the value is more than 2GB. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add marvell sdhci driverLei Wen2011-07-15-0/+22
| | | | | | | | | This could support both armada100 and pantheon serial in the mainline, while this driver also be tested to support upcoming mg, mmp2 and mmp3 hardware. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add sdhci generic frameworkLei Wen2011-07-15-0/+434
| | | | | | | | | Nowdays, there are plenty of mmc driver in uboot adopt the sd standard host design, aka as sdhci. It is better to centralize the common logic together to better maintenance. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* MMC: add erase function to both mmc and sdLei Wen2011-07-15-0/+102
| | | | | | | | | | | Erase is a very basic function since the begin of sd specification is announced. Although we could write a bulk of full 0xff memory to the range to take place of erase, it is more convenient and safe to implement the erase function itself. Signed-off-by: Lei Wen <leiwen@marvell.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mike Frysinger <vapier@gentoo.org>
* mmc: Tegra2: SD/MMC driver for Seaboard - eMMC on SDMMC4, SDIO on SDMMC3Tom Warren2011-07-15-0/+592
| | | | | Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Andy Fleming <afleming@freescale.com>
* S5P: add set_mmc_clk for external clock controlJaehoon Chung2011-05-26-0/+4
| | | | | | | | | | | This patch added set_mmc_clk for external clock control. c210 didn't support host clock control. So We need external_clock_control function for c210. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* MMC S5P: Fix typoDirk Behme2011-05-26-1/+1
| | | | | | | | | | | | | | | Fix typo resulting in the compilation error s5p_mmc.c: In function 's5p_mmc_initialize': s5p_mmc.c:469: error: 'struct mmc' has no member named 'm_bmax' introduced by commit "MMC: make b_max unconditional" (8feafcc49c0b7a9c541904f95a43dbef2fecc38b) Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: John Rigby <john.rigby@linaro.org> CC: Andy Fleming <afleming@freescale.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Minor coding style cleanup.Wolfgang Denk2011-05-19-4/+4
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MMC: omap_hsmmc.c: Add missing prototype headerDirk Behme2011-05-18-0/+1
| | | | | | | | | | | | | | | | Add missing header file to fix compilation warning omap_hsmmc.c: In function 'omap_mmc_init': omap_hsmmc.c:474: warning: implicit declaration of function 'get_cpu_family' omap_hsmmc.c:474: warning: implicit declaration of function 'get_cpu_rev' introduced by commit "MMC: omap_hsmmc.c: disable multiblock rw on old rev omap34xx silicon" (4ca9244d74f146a0605f5bee28a66e39aae88d3e) Signed-off-by: Dirk Behme <dirk.behme@googlemail.com> CC: Andy Fleming <afleming@freescale.com> CC: John Rigby <john.rigby@linaro.org>
* fsl_esdhc: Initialize mmc->b_maxFabio Estevam2011-05-18-0/+1
| | | | | | | commit 262951(MMC: make b_max unconditional) missed to update fsl_esdhc. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* mmc: enable partition switch function for emmcLei Wen2011-05-18-1/+29
| | | | | | | | | | | | | | | | | | | For emmc, it may have up to 7 partitions: two boot partitions, one user partition, one RPMB partition and four general purpose partitions. (Refer to JESD84-A44.pdf/page 154) As bootloader may need to read out or reflashing images on those different partitions, it is better to enable the partition switch with console command support. Also for partition would be restore to user partition(part 0) when CMD0 is used, so change mmc_init routine to perform normal initialization only once for each slot, unless use the rescan command to force init again. Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* cmd_mmc: eliminate device num in the mmc commandLei Wen2011-05-18-0/+5
| | | | | | | mmc command applied device, like ide and usb... Signed-off-by: Lei Wen <leiwen@marvell.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mmc_spi: generate response for send status commandThomas Chou2011-05-18-0/+5
| | | | | | | | | | A "send status" command is added with the commit "mmc: checking status after commands with R1b response". But the status register returned from send status command of SPI protocol is different from that of MMC/SD protocol. We do a simple test and generate a response in stead of full bit-by-bit translation. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* ATMEL: fix related common atmel driver filesReinhard Meyer2011-05-18-1/+1
| | | | Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de>
* avr32: fixup definitions to ATMEL_BASE_xxxAndreas Bießmann2011-05-18-2/+2
| | | | Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* avr32: rename memory-map.h -> hardware.hAndreas Bießmann2011-05-18-1/+1
| | | | Signed-off-by: Andreas Bießmann <biessmann@corscience.de>
* fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2Jason Liu2011-04-29-0/+4
| | | | | | | | | | | | | | | | | | | | For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. This is a software Software Restrictions in i.MX53 reference manual: 29.7.8 Multi-block Read For pre-defined multi-block read operation, that is,the number of blocks to read has been defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without abort command at card side, an abort command, either automatic or manual CMD12/CMD52, is still required by ESDHC after the pre-defined number of blocks are done, to drive the internal state machine to idle mode. In this case, the card may not respond to this extra abort command and ESDHC will get Response Timeout. It is recommended to manually send an abort command with RSPTYP[1:0] both bits cleared. Signed-off-by: Jason Liu <jason.hui@linaro.org>
* MMC: omap_hsmmc.c: disable multiblock rw on old rev omap34xx siliconJohn Rigby2011-04-29-0/+8
| | | | Signed-off-by: John Rigby <john.rigby@linaro.org>
* MMC: make b_max unconditionalJohn Rigby2011-04-29-6/+16
| | | | | | | | | | | | | | Make existing field b_max field in struct mmc unconditional and use it instead of CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_bread and mmc_bwrite. Initialize b_max to CONFIG_SYS_MMC_MAX_BLK_COUNT in mmc_register if it has not been initialized by the hw driver. Initialize b_max to 0 in all callers to mmc_register. Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MMC: Add support for PL180 ARM mmc deviceMatt Waddel2011-04-29-0/+625
| | | | | | | Add support for the ARM PrimeCell MultiMedia Interface - PL180. Ported from original device driver written by ST-Ericsson. Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
* MMC may wrongly regconize 2GB eMMC as high capacityRaffaele Recalcati2011-04-13-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Hi Terry, > So I guess: > mmc_init calls mmc_send_op_cond  that set  high_capacity, > than it calls mmc_startup, that, with MMC_CMD_SEND_CSD  command, set > the capacity, using values in CSD register. > So I guess that mmc_change_freq should not recalculate high_capacity. > > It seems better, isn't it? > > Regards, > Raffaele > Finally I think that it is enough to apply the following patch in order to fix the issue. Regards, Raffaele Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: trace addedRaffaele Recalcati2011-04-13-0/+57
| | | | | | | | | | Defining CONFIG_MMC_TRACE in the include board file it is possible to activate a tracing support. This code helps in case of eMMC hw failure or to investigate possible eMMC initialization issues. Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: SEND_OP_COND considers card capabilities (voltage)Raffaele Recalcati2011-04-13-3/+18
| | | | | | | | | | | The first SEND_OP_COND (CMD1) command added is used to ask card capabilities. After it an AND operation is done between card capabilities and host capabilities (at the moment only for the voltage field). Finally the correct value is sent to the MMC, waiting that the card exits from busy state. Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: checking status after commands with R1b responseRaffaele Recalcati2011-04-13-3/+59
| | | | | | | | | | It is recommended to check card status after these kind of commands. This is done using CMD13 (SEND_STATUS) JEDEC command until the card is ready. In case of error the card status field is displayed. Signed-off-by: Raffaele Recalcati <raffaele.recalcati@bticino.it> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: remove duplicated header fileMinkyu Kang2011-04-13-1/+0
| | | | | Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: add generic mmc spi driverThomas Chou2011-04-13-20/+354
| | | | | | | | | | | | | This patch supports mmc/sd card with spi interface. It is based on the generic mmc framework. It works with SDHC and supports multi blocks read/write. The crc checksum on data packet is enabled with the def, There is a subcomamnd "mmc_spi" to setup spi bus and cs at run time. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mmc: constify & localize dataMike Frysinger2011-04-13-2/+2
| | | | | | | These local vars need not be writable nor exported. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* drivers/mmc/fsl_esdhc.c: reordered testsFrans Meulenbroeks2011-04-13-3/+3
| | | | | | | | | | | | As DATA_ERROR includes the value IRQSTAT_DTOE, a timeout error would yield the first error return instead of TIMEOUT. By swapping the test TIMEOUTs are reported as such An alternate solution would be to remove the IRQSTAT_DTOE from the DATA_ERROR define but as that one might be less desired I've opted for the simplest solution Signed-off-by: Frans Meulenbroeks <fransmeulenbroeks@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MMC: Max blocks value adjustableMatt Waddel2011-04-13-10/+9
| | | | | | | | | | The maximum blocks value was hardcoded to 65535 due to a 16 bit register length. The value can change for different platforms. This patch makes the default the current value of 65535, but it is configurable for other platforms. Signed-off-by: Matt Waddel <matt.waddel@linaro.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* SD1.00 wide-bus fixAlagu Sankar2011-04-13-3/+3
| | | | | | Fixed a bug wherein SD version 1.0 cards were not configured for 4-bit mode Signed-off-by: Alagu Sankar <alagusankar@embwise.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-10-4/+4
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| * fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-10-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Blackfin: bfin_sdh: add support for multiblock operationsSonic Zhang2011-04-08-4/+5
| | | | | | | | | | | | | | Don't forget to count full data size for the multiblock operation request. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bfin_sdh: set all timer bits before transferCliff Cai2011-04-08-1/+1
| | | | | | | | | | | | | | | | The timer register is 32bits, not 16bit, so 0xFFFF won't fill it. Write out -1 to make sure to fill the whole thing. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: BF50x: new processor portMike Frysinger2011-04-08-1/+1
|/ | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* S5P: mmc: Resolved interrupt error during mmc_initChander Kashyap2011-03-27-1/+1
| | | | | | | | | | | | Blocksize was hardcoded to 512 bytes. But the blocksize varies depeding on various mmc subsystem commands (between 8 and 512). This hardcoding was resulting in interrupt error during data transfer. It is now calculated based upon the request sent by mmc subsystem. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* fsl_esdhc: Correcting esdhc timeout counter calculationPriyanka Jain2011-03-07-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | - Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout, Timeout period = (2^(timeout + 13)) SD Clock cycles - As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec. - Number of SD Clock cycles for 0.25sec should be minimum (SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles - Calculating timeout based on (2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC-A001 (enable on P2020)Kumar Gala2011-02-03-0/+5
| | | | | | | Data timeout counter (SYSCTL[DTOCV]) is not reliable for values of 4, 8, and 12. Program one more than the desired value: 4 -> 5, 8 -> 9, 12 -> 13. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Minor Coding Style Cleanup.Wolfgang Denk2011-02-02-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Davinci MMCSD SupportSandeep Paulraj2011-02-02-0/+405
| | | | | | | | | | Added support for MMC/SD cards for Davinci. This feature is enabled by CONFIG_DAVINCI_MMC and is dependant on CONFIG_MMC and CONFIG_GENERIC_MMC options. This is tested on DM355 and DM365 EVMs with both the available mmc controllers. Signed-off-by: Alagu Sankar <alagusankar@embwise.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* fsl_esdhc: Add the workaround for erratum ESDHC135 (enable on P4080)Roy Zang2011-01-14-0/+5
| | | | | | | | | | | The default value of the SRS, VS18 and VS30 and ADMAS fields in the host controller capabilities register (HOSTCAPBLT) are incorrect. The default of these bits should be zero instead of one. Clear these bits out when we read HOSTCAPBLT. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Add the workaround for erratum ESDHC111 (enable on P4080)Jerry Huang2011-01-14-1/+9
| | | | | | | | | Do not issue a manual asynchronous CMD12. Instead, use a (software) synchronous CMD12 or AUTOCMD12 to abort data transfer. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Fix esdhc disabled problem on some platformsChenhui Zhao2011-01-14-6/+8
| | | | | | | | | | | | Some new platform's esdhc pins don't share with other function. The eSDHC shouldn't be disabled, even if "esdhc" isn't defined in hwconfig env variable. Use CONFIG_FSL_ESDHC_PIN_MUX to fix this problem. Signed-off-by: Chenhui Zhao <b26998@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_esdhc: Fix the voltage validation processLi Yang2010-12-18-5/+15
| | | | | | | | | | | The current code use all the voltage range support by the host controller to do the validation. This will cause problem when the host supports Low Voltage Range. Change the validation voltage to be based on board setup. Signed-off-by: Li Yang <leoli@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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